Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
246
Freescale
Semiconductor
Read: Anytime
Write: Refer to each bit for individual write conditions
Module Base + 0x0007
7
6
5
4
3
2
1
0
R
RTIF
0
0
LOCKIF
LOCK
0
OSCIF
UPOSC
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-8. S12CPMU_UHV_V5 Flags Register (CPMUIFLG)
Table 7-5. CPMUIFLG Field Descriptions
Field
Description
7
RTIF
Real Time Interrupt Flag
— RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
4
LOCKIF
PLL Lock Interrupt Flag
—
LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
3
LOCK
Lock Status Bit
—
LOCK reflects the current state of PLL lock condition. Writes have no effect.
While PLL is
unlocked (LOCK=0) f
PLL
is f
VCO
/ 4 to protect the system from high core clock frequencies during the PLL
stabilization time t
lock
.
0 VCOCLK is not within the desired tolerance of the target frequency.
f
PLL
= f
VCO
/4.
1 VCOCLK is within the desired tolerance of the target frequency.
f
PLL
= f
VCO
/(1).
1
OSCIF
Oscillator Interrupt Flag
—
OSCIF is set to 1 when UPOSC status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect. If enabled (OSCIE=1), OSCIF causes an interrupt request.
0 No change in UPOSC bit.
1 UPOSC bit has changed.
0
UPOSC
Oscillator Status Bit
— UPOSC reflects the status of the oscillator. Writes have no effect. Entering Full Stop
Mode UPOSC is cleared.
0 The oscillator is off or oscillation is not qualified by the PLL.
1 The oscillator is qualified by the PLL.
