Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
Freescale Semiconductor
283
Figure 7-38. Full Stop Mode using Oscillator Clock as source of the Bus Clock
Depending on the COP configuration there might be an additional significant latency time until COP is
active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time
occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for
details).
CPU
UPOSC
t
lock
STOP instruction
execution
interrupt
continue execution
wake up
t
STP_REC
Core
Clock
select OSCCLK as Core/Bus Clock by writing PLLSEL to “0”
PLLSEL
automatically set when going into Full Stop Mode
OSCCLK
PLLCLK
crystal/resonator starts oscillating
t
UPOSC
