Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
207
accesses). Furthermore, comparators A and C can compare the data buses to values stored in DBGXD3-0
and allow data bit masking.
The comparators can monitor the buses for an exact address or an address range. The comparator
configuration is controlled by the control register contents and the range control by the DBGC2 contents.
The comparator control register also allows the type of data access to be included in the comparison
through the use of the RWE and RW bits. The RWE bit controls whether the access type is compared for
the associated comparator and the RW bit selects either a read or write access for a valid match.
The INST bit in each comparator control register is used to determine the matching condition. By setting
INST, the comparator matches opcode addresses, whereby the databus, data mask, RW and RWE bits are
ignored. The comparator register must be loaded with the exact opcode address.
The comparator can be configured to match memory access addresses by clearing the INST bit.
Each comparator match can force a transition to another state sequencer state (see
).
Once a successful comparator match has occurred, the condition that caused the original match is not
verified again on subsequent matches. Thus if a particular data value is matched at a given address, this
address may not contain that data value when a subsequent match occurs.
Comparators C and D can also be used to select an address range to trace from, when tracing CPU accesses
in Detail mode. This is determined by the TRANGE bits in the DBGTCRH register. The TRANGE
encoding is shown in
. If the TRANGE bits select a range definition using comparator D and the
COMPE bit is clear, then comparator D is configured for trace range definition. By setting the COMPE bit
the comparator is configured for address bus comparisons, the TRANGE bits are ignored and the tracing
range function is disabled. Similarly if the TRANGE bits select a range definition using comparator C and
the COMPE bit is clear, then comparator C is configured for trace range definition.
Match[0, 1, 2, 3] map directly to Comparators [A, B, C, D] respectively, except in range modes (see
). Comparator priority rules are described in the event priority section (
.
6.4.2.1
Exact Address Comparator Match
With range comparisons disabled, the match condition is an exact equivalence of address bus with the
value stored in the comparator address registers. Qualification of the type of access (R/W) is also possible.
Code may contain various access forms of the same address, for example a 16-bit access of ADDR[n] or
byte access of ADDR[n+1] both access n+1. The comparators ensure that any access of the address defined
by the comparator address register generates a match, as shown in the example of
. Thus if the
comparator address register contains ADDR[n+1] any access of ADDR[n+1] matches. This means that a
16-bit access of ADDR[n] or 32-bit access of ADDR[n-1] also match because they also access
ADDR[n+1]. The right hand columns show the contents of DBGxA that would match for each access.
Table 6-41. Comparator Address Bus Matches
Access
Address
ADDR[n]
ADDR[n+1]
ADDR[n+2]
ADDR[n+3]
32-bit
ADDR[n]
Match
Match
Match
Match
16-bit
ADDR[n]
Match
Match
No Match
No Match
16-bit ADDR[n+1]
No
Match
Match
Match
No Match
