Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
414 Freescale Semiconductor
10.8.5 List Usage — CSL double buffer mode and RVL double buffer mode
In this use case both list types are configured for double buffer mode (CSL_BMOD=1’b1) and
RVL_BMOD=1’b1).
This setup is the same as Section 10.8.3, “List Usage — CSL double buffer mode and RVL double buffer
mode but at the end of a CSL the CSL is not always swapped (bit LDOK not always set with bit RSTA).
The Result Value List is swapped whenever a CSL is finished or a CSL got aborted.
Figure 10-39. CSL Double Buffer Mode — RVL Double Buffer Mode Diagram
10.8.6 RVL swapping in RVL double buffer mode and related registers
ADCIMDRI and ADCEOLRI
When using the RVL in double buffer mode, the registers ADCIMDRI and ADCEOLRI can be used by
the application software to identify which RVL holds relevant and latest data and which CSL is related to
this data. These registers are updated at the setting of one of the CON_IF[15:1] or the EOL_IF interrupt
flags. As described in the register description
Section 10.4.2.13, “ADC Intermediate Result Information
Register (ADCIMDRI) and Section 10.4.2.14, “ADC End Of List Result Information Register
(ADCEOLRI) , the register ADCIMDRI, for instance, is always updated at the occurrence of a
CON_IF[15:1] interrupt flag amongst other cases. Also each time the last conversion command of a CSL
is finished and the corresponding result is stored, the related EOL_IF flag is set and register ADCEOLRI
is updated. Hence application software can pick up conversion results, or groups of results, or an entire
result list driven fully by interrupts. A use case example diagram is shown in
Figure 10-40 .
CSL_0
CSL_1
RVL_0
RVL_1