Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
381
10.4.2.13 ADC Intermediate Result Information Register (ADCIMDRI)
This register is cleared when bit ADC_SR is set or bit ADC_EN is clear.
Read: Anytime
Write: Never
NOTE
The register ADCIMDRI is updated and simultaneously a conversion
interrupt flag CON_IF[15:1] occurs when the corresponding conversion
command (conversion command with INTFLG_SEL[3:0] set) has been
processed and related data has been stored to RAM.
Module Base + 0x000E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CSL_IMD RVL_IMD
0
0
0
0
0
0
0
0
RIDX_IMD[5:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-16. ADC Intermediate Result Information Register (ADCIMDRI)
Table 10-17. ADCIMDRI Field Descriptions
Field
Description
15
CSL_IMD
Active CSL At Intermediate Event
— This bit indicates the active (used) CSL at the occurrence of a conversion
interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event) or when a Sequence Abort
Event gets executed.
0 CSL_0 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set.
1 CSL_1 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set.
14
RVL_IMD
Active RVL At Intermediate Event
— This bit indicates the active (used) RVL buffer at the occurrence of a
conversion interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event) or when a
Sequence Abort Event gets executed.
0 RVL_0 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set.
1 RVL_1 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set.
5-0
RIDX_IMD[5:0]
RES_IDX Value At Intermediate Event
— These bits indicate the result index (RES_IDX) value at the
occurrence of a conversion interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event)
or occurrence of EOL_IF flag or when a Sequence Abort Event gets executed to abort an ongoing conversion
(the result index RES_IDX is captured at the occurrence of a result data store).
When a Sequence Abort Event has been processed flag SEQAD_IF is set and the RES_IDX value of the last
stored result is provided. Hence in case an ongoing conversion is aborted the RES_IDX value captured in
RIDX_IMD bits depends on bit STORE_SEQA:
- STORE_SEQA =1: The result index of the aborted conversion is provided
- STORE_SEQA =0: The result index of the last stored result at abort execution time is provided
In case a CSL is aborted while no conversion is ongoing (ADC waiting for a Trigger Event) the last captured result
index is provided.
In case a Sequence Abort Event was initiated by hardware due to MCU entering Stop Mode or Wait Mode with
bit SWAI set, the result index of the last stored result is captured by bits RIDX_IMD but flag SEQAD_IF is not set.
