Chapter 4 Interrupt (S12ZINTV0)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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Freescale Semiconductor
bit in the CCW set, the associated ISR is not called. The CPU then resumes program execution with the
instruction following the WAI or STOP instruction. This feature works following the same rules like any
interrupt request, i.e. care must be taken that the X-bit maskable interrupt request used for wake-up
remains active at least until the system begins execution of the instruction following the WAI or STOP
instruction; otherwise, wake-up may not occur.
1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is
shared with other peripheral modules on the device. Please refer to the Port Integration Module (PIM) section of the MCU
reference manual for details.
