Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 1 Device Overview MC9S12ZVHY/MC9S12ZVHL Families
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 67
1.12 COP Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register are loaded from the
Flash configuration field byte at global address 0xFF_FE0E
during the reset sequence. See Table 1-12 and
Table 1-13 for coding
1.13 ADC0 Internal Channels
Table 1-14 lists the internal sources which are connected to these special conversion channels.
Table 1-12. Initial COP Rate Configuration
NV[2:0] in
FOPT Register
CR[2:0] in
COPCTL Register
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000
Table 1-13. Initial WCOP Configuration
NV[3] in
FOPT Register
WCOP in
COPCTL Register
1 0
0 1