Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 12 Serial Communication Interface (S12SCIV6)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 485
12.3.2.5 SCI Alternative Control Register 2 (SCIACR2)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Module Base + 0x0002
7 6 5 4 3 2 1 0
R
IREN TNP1 TNP0
0 0
BERRM1 BERRM0 BKDFE
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 12-8. SCI Alternative Control Register 2 (SCIACR2)
Table 12-7. SCIACR2 Field Descriptions
Field Description
7
IREN
Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule.
0 IR disabled
1 IR enabled
6:5
TNP[1:0]
Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow
pulse. See Table 12-8 .
2:1
BERRM[1:0]
Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 12-9 .
0
BKDFE
Break Detect Feature Enable — BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
1 Break detect circuit enabled
Table 12-8. IRSCI Transmit Pulse Width
TNP[1:0] Narrow Pulse Width
11 1/4
10 1/32
01 1/16
00 3/16
Table 12-9. Bit Error Mode Coding
BERRM1 BERRM0 Function
0 0 Bit error detect circuit is disabled
0 1 Receive input sampling occurs during the 9th time tick of a transmitted bit
(refer to
Figure 12-19 )
1 0 Receive input sampling occurs during the 13th time tick of a transmitted bit
(refer to
Figure 12-19 )
1 1 Reserved