Chapter 18 Real-Time Counter With Calendar (RTCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
652
Freescale Semiconductor
and temperature etc factors, the RTCPS is set to 15, the RTCCLK frequency will be 31187.5HZ. We set
RTCMOD value to 31187 first. The fraction value will be 0.5, and we can get CCS=0, Q=3 or CCS=1,
Q=8 or CCS=2, Q=15 or CCS=3, Q=30.
18.5.5 Calendar Register and Bit Write Protection
A write-protect mechanism is implemented to prevent accidental writes to the RTC clock registers, calen-
dar registers, and other control bits. The protected RTC registers and bits are listed in below table
The mechanism uses the RTCWE[1:0] bits in the RTC control register 3(RTCCTL3) in a state machine,
which requires a bit-write sequence to disable the write-protection. A block diagram of the state machine
is shown in below Figure.
Table 18-15. Write-Protected RTC Registers and Bits
Register
Bit
RTC Control Register 1(RTCCTL1)
All Bits
Second Register(RTCSECR)
All Bits
Minute Register(RTCMINR)
All Bits
Hour Register(RTCHRR)
All Bits
Wri
te 0
1 to
RT
CW
E
Write 10 to RTCWE
Write an
y value o
ther than
10 to RT
CWE
Write an
y value o
ther than
11 to RT
CWE
W
rite
11
to
R
TCW
E
Write-Protect ENABLED
W
rite
an
y v
alu
e o
the
r
W
rite
00
to
R
TC
W
E
RTCWE = 11
RTCWE = 10
RESET
Write any value
other than 00
to RTWE
RTCWE = 00
RTCWE 01
Write any value
other than 10
to RTWE
tha
n 0
1 to
R
TC
W
E
Write-Protect
DISABLED
Wr
ite 1
0 to
RT
CW
E
Note: Reading RTCWE[1:0]
always return 00.
