Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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In the case of simultaneous matches, the match on the higher channel number (3...0) has priority.
6.3.2.9 Debug State Control Register 3 (DBGSCR3)
Read: Anytime.
Write: If DBG is not armed and PTACT is clear.
The state control register three selects the targeted next state whilst in State3. The matches refer to the
outputs of the comparator match control logic as depicted in
Figure 6-1 and described in Section 6.3.2.12” .
Comparators must be enabled by setting the comparator enable bit in the associated DBGxCTL control
register.
5–4
C2SC[1:0]
Channel 2 State Control.
These bits select the targeted next state whilst in State2 following a match2.
7–6
C3SC[1:0]
Channel 3 State Control.
If EEVE !=10, these bits select the targeted next state whilst in State2 following a match3.
If EEVE =10, these bits select the targeted next state whilst in State2 following an external event.
Table 6-19. State2 Match State Sequencer Transitions
CxSC[1:0] Function
00 Match has no effect
01 Match forces sequencer to State1
10 Match forces sequencer to State3
11 Match forces sequencer to Final State
Address: 0x0109
7 6 5 4 3 2 1 0
R
C3SC1 C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0
W
Reset 0 0 0 0 0 0 0 0
Figure 6-11. Debug State Control Register 3 (DBGSCR3)
Table 6-20. DBGSCR3 Field Descriptions
Field Description
1–0
C0SC[1:0]
Channel 0 State Control.
These bits select the targeted next state whilst in State3 following a match0.
3–2
C1SC[1:0]
Channel 1 State Control.
These bits select the targeted next state whilst in State3 following a match1.
5–4
C2SC[1:0]
Channel 2 State Control.
These bits select the targeted next state whilst in State3 following a match2.
Table 6-18. DBGSCR2 Field Descriptions (continued)
Field Description