Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
196 Freescale Semiconductor
6.3.2.12 Debug Comparator A Control Register (DBGACTL)
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
Table 6-26 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if
INST is set, because matches based on opcodes reaching the execution stage are data independent.
101,110,111 Reserved
Address: 0x0110
7 6 5 4 3 2 1 0
R 0
NDB INST
0
RW RWE reserved COMPE
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 6-14. Debug Comparator A Control Register
Table 6-25. DBGACTL Field Descriptions
Field Description
6
NDB
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
register value or when the data bus differs from the register value. This bit is ignored if the INST bit in the
same register is set.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
5
INST
Instruction Select — This bit configures the comparator to compare PC or data access addresses.
0 Comparator compares addresses of data accesses
1 Comparator compares PC address
3
RW
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator. The RW bit is ignored if RWE is clear or INST is set.
0 Write cycle is matched
1 Read cycle is matched
2
RWE
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator. This bit is ignored when INST is set.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
0
COMPE
Enable Bit — Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled
Table 6-24. SSF[2:0] — State Sequence Flag Bit Encoding
SSF[2:0] Current State