Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
370
Freescale Semiconductor
10.4.2.6
ADC Conversion Flow Control Register (ADCFLWCTL)
Bit set and bit clear instructions should not be used to access this register.
When the ADC is enabled the bits of ADCFLWCTL register can be modified after a latency time of three
Bus Clock cycles.
All bits are cleared if bit ADC_EN is clear or via ADC soft-reset.
Read: Anytime
Write:
•
Bits SEQA, TRIG, RSTA, LDOK can only be set if bit ADC_EN is set.
•
Writing 1’b0 to any of these bits does not have an effect
Timing considerations (Trigger Event - channel sample start) depending on ADC mode configuration:
•
Restart Mode
When the Restart Event has been processed (initial command of current CSL is loaded) it takes two
Bus Clock cycles plus two ADC conversion clock cycles (pump phase) from the Trigger Event (bit
TRIG set) until the select channel starts to sample.
During a conversion sequence (back to back conversions) it takes five Bus Clock cycles plus two
ADC conversion clock cycles (pump phase) from current conversion period end until the newly
selected channel is sampled in the following conversion period.
•
Trigger Mode
When a Restart Event occurs a Trigger Event is issued simultaneously. The time required to process
the Restart Event is mainly defined by the internal read data bus availability and therefore can vary.
In this mode the Trigger Event is processed immediately after the Restart Event is finished and both
conversion flow control bits are cleared simultaneously. From de-assert of bit TRIG until sampling
begins five Bus Clock cycles are required. Hence from occurrence of a Restart Event until channel
sampling it takes five Bus Clock cycles plus an uncertainty of a few Bus Clock cycles.
For more details regarding the sample phase please refer to
Section 10.5.2.2, “Sample and Hold Machine
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
SEQA
TRIG
RSTA
LDOK
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-9. ADC Conversion Flow Control Register (ADCFLWCTL)
