Chapter 13 Serial Peripheral Interface (S12SPIV5)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
527
Figure 13-9. Reception with SPIF serviced in Time
Figure 13-10. Reception with SPIF serviced too late
13.4
Functional Description
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral
devices. Software can poll the SPI status flags or SPI operation can be interrupt driven.
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set,
the four associated SPI port pins are dedicated to the SPI function as:
•
Slave select (SS)
•
Serial clock (SCK)
•
Master out/slave in (MOSI)
•
Master in/slave out (MISO)
Receive Shift Register
SPIF
SPI Data Register
Data A
Data B
Data A
Data A Received
Data B Received
Data C
Data C
SPIF Serviced
Data C Received
Data B
= Unspecified
= Reception in progress
Receive Shift Register
SPIF
SPI Data Register
Data A
Data B
Data A
Data A Received
Data B Received
Data C
Data C
SPIF Serviced
Data C Received
Data B Lost
= Unspecified
= Reception in progress
