Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 2 Port Integration Module (S12ZVHYPIMV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
90 Freescale Semiconductor
2.3.2 Register Descriptions
This section describes the details of all configuration registers.
• If not stated differently, writing to reserved bits has no effect and read returns zero.
• All register read accesses are synchronous to internal clocks.
• All registers can be written at any time, however a specific configuration might not become active.
E.g. a pullup device does not become active while the port is used as a push-pull output.
• General-purpose data output availability depends on prioritization; input data registers always
reflect the pin status independent of the use.
• Pull-device availability, pull-device polarity, wired-or mode, key-wake up functionality are
independent of the prioritization unless noted differently.
• The description of registers PTx, PTIx, DDRx, DIENx, PERx, PPSx, SRRx, WOMx, PIEx and
PIFx generically assumes a fully implemented 8-bit register. For availability of individual bits refer
to
Section 2.3.1, “Register Map“ ”.
0x0352 DDRU
R
DDRU7 DDRU6 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0
W
0x0353 PERU
R
PERU7 PERU6 PERU5 PERU4 PERU3 PERU2 PERU1 PERU0
W
0x0354 PPSU
R
PPSU7 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0
W
0x0355–
0x035D
Reserved
R 0 0 0 0 0 0 0 0
W
0x035E SRRU
R
SRRU7 SRRU6 SRRU5 SRRU4 SRRU3 SRRU2 SRRU1 SRRU0
W
0x035F Reserved
R 0 0 0 0 0 0 0 0
W
0x0360–
0x037F
Reserved
R 0 0 0 0 0 0 0 0
W
Global
Address
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0