Chapter 2 Port Integration Module (S12ZVHYPIMV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
105
2.3.2.17
Wired-Or Mode Register
2.3.2.18
Port Interrupt Enable Register
Read: Anytime
Address 0x023E WOMA
0x02DF WOMS
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
WOMx7
WOMx6
WOMx5
WOMx4
WOMx3
WOMx2
WOMx1
WOMx0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-19. Wired-Or Mode Register
Table 2-17. Wired-Or Mode Register Field Descriptions
Field
Description
7-0
WOMx
Wired-Or Mode
— Enable open-drain output
This bit configures the output pin as wired-or. If enabled the output is driven active low only (open-drain) while the
active high drive is turned off. This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs. Enable the IIC0, it will force the corresponding pins to be open drain output.
1 Output buffers operate as open-drain outputs
0 Output buffers operate as push-pull outputs
Address 0x02C6 PIET
0x02D6 PIES
0x028D PIEADL
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
PIEx7
PIEx6
PIEx5
PIEx4
PIEx3
PIEx2
PIEx1
PIEx0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-20. Port Interrupt Enable Register
Table 2-18. Port Interrupt Enable Register Field Descriptions
Field
Description
7-0
PIEx
Port Interrupt Enable
— Activate pin interrupt
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
