Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 353
Chapter 10
Analog-to-Digital Converter (ADC12B_LBA_V1)
10.1 Introduction
The ADC12B_LBA is an n-channel multiplexed input successive approximation analog-to-digital
converter. Refer to device electrical specifications for ADC parameters and accuracy.
The List Based Architecture (LBA) provides flexible conversion sequence definition as well as flexible
oversampling. The order of channels to be converted can be freely defined. Also, multiple instantiations
of the module can be triggered simultaneously (matching sampling point across multiple module
instantiations).
There are four register bits which control the conversion flow (please refer to the description of register
ADCFLWCTL).
The four conversion flow control bits of register ADCFLWCTL can be modified in two different ways:
• Via data bus accesses
• Via internal interface Signals (Trigger, Restart, LoadOK, and Seq_Abort; see also Figure 10-2 ).
Each Interface Signal is associated with one conversion flow control bit.
For information regarding internal interface connectivity related to the conversion flow control please
refer to the device overview of the reference manual.
The ADCFLWCTL register can be controlled via internal interface only or via data bus only or by both
depending on the register access configuration bits ACC_CFG[1:0].
Table 10-1. Revision History
Revision
Number
Revision
Date
Sections Affected Description of Changes
V1.35 06. Nov 2012 10.4.2.9/10-376 Modified bit description of flag LDOK_EIF for better understanding.
V1.36 08 Nov 2012 10.4.2.13/10-381 Updated description of bits RIDX_IMD for better understanding.
V1.37 19. Apr 2013 - Updates from review of reference manual to fix typos etc.
V1.38 30. Apr 2013 10.4.2.13/10-381
Provided more detailed information regarding captured information in
bits RIDX_IMD[5:0] for different scenarios of Sequence Abort Event
execution.
V1.39 02. Jul 2013 10.4.2.6/10-370 Update of: Timing considerations for Restart Mode
V1.40 02. Oct 2013 entire document
Updated formatting and wording correction for entire document (for
technical publications).