Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
206 Freescale Semiconductor
6.4 Functional Description
This section provides a complete functional description of the DBG module.
6.4.1 DBG Operation
The DBG module operation is enabled by setting ARM in DBGC1. When armed it supports storing of data
in the trace buffer and can be used to generate breakpoints to the CPU. The DBG module is made up of
comparators, control logic, the trace buffer, and the state sequencer,
Figure 6-1 .
The comparators monitor the bus activity of the CPU. Comparators can be configured to monitor opcode
addresses (effectively the PC address) or data accesses. Comparators can be configured during data
accesses to mask out individual data bus bits and to use R/W access qualification in the comparison.
Comparators can be configured to monitor a range of addresses.
When configured for data access comparisons, the match is generated if the address (and optionally data)
of a data access matches the comparator value.
Configured for monitoring opcode addresses, the match is generated when the associated opcode reaches
the execution stage of the instruction queue, but before execution of that opcode.
When a match with a comparator register value occurs, the associated control logic can force the state
sequencer to another state (see
Figure 6-26 ).
The state sequencer can transition freely between the states 1, 2 and 3. On transition to Final State bus
tracing can be triggered. On completion of tracing the state sequencer enters State0. If tracing is disabled
or End aligned tracing is enabled then the state sequencer transitions immediately from Final State to
State0. The transition to State0 generates breakpoints if breakpoints are enabled.
Independent of the comparators, state sequencer transitions can be forced by the external event input or by
writing to the TRIG bit in the DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads.
6.4.2 Comparator Modes
The DBG contains four comparators, A, B, C, and D. Each comparator compares the address stored in
DBGXAH, DBGXAM, and DBGXAL with the PC (opcode addresses) or selected address bus (data
15–0
DBGDA
[15:0]
Comparator Address Bits [15:0]— These comparator address bits control whether the comparator compares
the address bus bits [15:0] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Table 6-40. DBGDAH, DBGDAM, DBGDAL Field Descriptions
Field Description