Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
369
10.4.2.5
ADC Format Register (ADCFMT)
Read: Anytime
Write: Bits DJM and SRES[2:0] are writable if bit ADC_EN clear or bit SMOD_ACC set
Module Base + 0x0004
7
6
5
4
3
2
1
0
R
DJM
0
0
0
0
SRES[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-8. ADC Format Register (ADCFMT)
Table 10-7. ADCFMT Field Descriptions
Field
Description
7
DJM
Result Register Data Justification
— Conversion result data format is always unsigned. This bit controls
justification of conversion result data in the conversion result list.
0 Left justified data in the conversion result list.
1 Right justified data in the conversion result list.
2-0
SRES[2:0]
ADC Resolution Select
— These bits select the resolution of conversion results. See
for coding.
Table 10-8. Selectable Conversion Resolution
SRES[2]
SRES[1]
SRES[0]
ADC Resolution
0
0
0
8-bit data
0
0
1
Reserved
0
1
0
10-bit data
0
1
1
Reserved
1
0
0
12-bit data
1
x
x
Reserved
(1)
1. Reserved settings cause a severe error at ADC conversion start whereby
the CMD_EIF flag is set and ADC ceases operation
