Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
278
Freescale
Semiconductor
7.3.2.26
S12CPMU_UHV_V5 Oscillator Register 2 (CPMUOSC2)
This registers configures the external oscillator (XOSCLCP).
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write
has no effect.
Module Base + 0x001E
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
OMRE
OSCMOD
W
Reset
0
0
0
0
0
0
0
0
Figure 7-35. S12CPMU_UHV_V5 Oscillator Register 2 (CPMUOSC2)
Table 7-32. CPMUOSC2 Field Descriptions
Field
Description
1
OMRE
This bit enables the oscillator clock monitor reset. If OSCE bit in CPMUOSC register is 1, then the OMRE bit can
not be changed (writes will have no effect).
0 Oscillator clock monitor reset is disabled
1 Oscillator clock monitor reset is enabled
0
OSCMOD
This bit selects the mode of the external oscillator (XOSCLCP)
If OSCE bit in CPMUOSC register is 1, then the OSCMOD bit can not be changed (writes will have no effect).
0 External oscillator configured for loop controlled mode (reduced amplitude on EXTAL and XTAL))
1 External oscillator configured for full swing mode (full swing amplitude on EXTAL and XTAL)
