Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
178
Freescale Semiconductor
5.4.11
Serial Communication Timeout
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If
BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command
was issued. In this case, the target waits for a rising edge on BKGD in order to answer the SYNC request
pulse. When the BDC detects the rising edge a soft reset is generated, whereby the current BDC command
is discarded. If the rising edge is not detected, the target keeps waiting forever without any timeout limit.
If a falling edge is not detected by the target within 512 clock cycles since the last falling edge, a timeout
occurs and the current command is discarded without affecting memory or the operating mode of the
MCU. This is referred to as a soft-reset. This timeout also applies if 512 cycles elapse between 2
consecutive ERASE_FLASH commands. The soft reset is disabled whilst the internal flash mass erase
operation is pending completion.
timeouts are also possible if a BDC command is partially issued, or data partially retrieved. Thus if a time
greater than 512 BDCSI clock cycles is observed between two consecutive negative edges, a soft-reset
occurs causing the partially received command or data retrieved to be discarded. The next negative edge
at the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDC
command, or the start of a SYNC request pulse.
5.5
Application Information
5.5.1
Clock Frequency Considerations
Read commands without status and without ACK must consider the frequency relationship between
BDCSI and the internal core clock. If the core clock is slow, then the internal access may not have been
carried out within the standard 16 BDCSI cycle delay period (DLY). The host must then extend the DLY
period or clock frequencies accordingly. Taking internal clock domain synchronizers into account, the
minimum number of BDCSI periods required for the DLY is expressed by:
#DLY > 3(f
(BDCSI clock)
/ f
(core clock)
) + 4
and the minimum core clock frequency with respect to BDCSI clock frequency is expressed by
Minimum f
(core clock)
= (3/(#DLY cycles -4))f
(BDCSI clock)
For the standard 16 period DLY this yields f
(core clock)
>= (1/4)f
(BDCSI clock)
