Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 383
10.4.2.15 ADC Command Register 0 (ADCCMD_0)
Read: Anytime
Write: Only writable if bit SMOD_ACC is set
(see also
Section 10.4.2.2, “ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more
details)
NOTE
If bit SMOD_ACC is set modifying this register must be done carefully -
only when no conversion and conversion sequence is ongoing.
Module Base + 0x0014
31 30 29 28 27 26 25 24
R
CMD_SEL
0 0
INTFLG_SEL[3:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 10-18. ADC Command Register 0 (ADCCMD_0)
Table 10-19. ADCCMD_0 Field Descriptions
Field Description
31-30
CMD_SEL[1:0]
Conversion Command Select Bits — These bits define the type of current conversion described in Table 10-
20 .
27-24
INTFLG_SEL[3:0]
Conversion Interrupt Flag Select Bits — These bits define which interrupt flag is set in the ADCIFH/L register
at the end of current conversion.The interrupt flags ADCIF[15:1] are selected via binary coded bits
INTFLG_SEL[3:0]. See also
Table 10-21
Table 10-20. Conversion Command Type Select
CMD_SEL[1] CMD_SEL[0] Conversion Command Type Description
0 0 Normal Conversion
0 1
End Of Sequence
(Wait for Trigger to execute next sequence or for a Restart)
1 0
End Of List
(Automatic wrap to top of CSL
and Continue Conversion)
1 1
End Of List
(Wrap to top of CSL and:
- In “Restart Mode” wait for Restart Event followed by a Trigger
- In “Trigger Mode” wait for Trigger or Restart Event)