Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
Freescale Semiconductor
265
7.3.2.18
Autonomous Periodical Interrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL)
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical
interrupt rate.
Read: Anytime
Write: Anytime if APIFE=0, Else writes have no effect.
The period can be calculated as follows depending on logical value of the APICLK bit:
APICLK=0: Period = 2*(APIR[15:0] + 1) * (ACLK Clock Period * 2)
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock Period
NOTE
For APICLK bit clear the first time-out period of the API will show a
latency time between two to three f
ACLK
cycles due to synchronous clock
gate release when the API feature gets enabled (APIFE bit set)
.
Module Base + 0x0014
7
6
5
4
3
2
1
0
R
APIR15
APIR14
APIR13
APIR12
APIR11
APIR10
APIR9
APIR8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-23. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)
Module Base + 0x0015
7
6
5
4
3
2
1
0
R
APIR7
APIR6
APIR5
APIR4
APIR3
APIR2
APIR1
APIR0
W
Reset
0
0
0
0
0
0
0
0
Figure 7-24. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)
Table 7-22. CPMUAPIRH / CPMUAPIRL Field Descriptions
Field
Description
15-0
APIR[15:0]
Autonomous Periodical Interrupt Rate Bits
— These bits define the time-out period of the API. See
for details of the effect of the autonomous periodical interrupt rate bits.
