Chapter 21 64 KB Flash Module (S12ZFTMRZ64K2KV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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Freescale Semiconductor
To guarantee the proper read timing from the Flash array, the FTMRZ64K2K FMU will control (i.e. pause)
the S12Z core accesses, considering that the MCU can be configured to fetch data at a faster frequency
than the Flash block can support. Right after reset the FTMRZ64K2K FMU will be configured to run with
the maximum amount of wait-states enabled; if the user application is setup to run at a slower frequency
the control bits FCNFG[WSTAT] (see
) can be configured by the user to disable the
generation of wait-states, so it does not impose a performance penalty to the system if the read timing of
the S12Z core is setup to be within the margins of the Flash block. For a definition of the frequency values
where wait-states can be disabled please look into the Reference Manual.
The following sequence must be followed when the transition from a higher frequency to a lower
frequency is going to happen:
•
Flash resets with wait-states enabled;
•
system frequency must be configured to the lower target;
•
user writes to FNCNF[WSTAT] to disable wait-states;
•
user reads the value of FPSTAT[WSTATACK], the new wait-state configuration will be effective
when it reads as 1;
•
user must re-write FCLKDIV to set a new value based on the lower frequency.
The following sequence must be followed on the contrary direction, going from a lower frequency to a
higher frequency:
•
user writes to FCNFG[WSTAT] to enable wait-states;
•
user reads the value of FPSTAT[WSTATACK], the new wait-state configuration will be effective
when it reads as 1;
•
user must re-write FCLKDIV to set a new value based on the higher frequency;
•
system frequency must be set to the upper target.
CAUTION
If the application is going to require the frequency setup to change, the value
to be loaded on register FCLKDIV will have to be updated according to the
new frequency value. In this scenario the application must take care to avoid
locking the value of the FCLKDIV register: bit FDIVLCK must not be set
if the value to be loaded on FDIV is going to be re-written, otherwise a reset
is going to be required. Please refer to
Section 21.3.2.1, “Flash Clock
Section 21.4.5.1, “Writing the FCLKDIV
21.4.4
Internal NVM resource
IFR is an internal NVM resource readable by CPU . The IFR fields are shown in
.
The NVM Resource Area global address map is shown in
21.4.5
Flash Command Operations
Flash command operations are used to modify Flash memory contents.
