Chapter 1 Device Overview MC9S12ZVHY/MC9S12ZVHL Families
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
66
Freescale Semiconductor
1.11.3
Effects of Reset
When a reset occurs, MCU registers and control bits are initialized. For RTC block, some registers are
power on reset only. Refer to the respective block sections for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers
1.11.3.1
Flash Configuration Reset Sequence Phase
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the
Section 21.6, “Initialization”
block.
1.11.3.2
Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.11.3.3
I/O Pins
Refer to
Chapter 2, “Port Integration Module (S12ZVHYPIMV1)
for reset configurations of all peripheral
module ports.
1.11.3.4
RAM
The system RAM arrays, including their ECC syndromes, are initialized following a power on reset, but
not out of warm reset. All other RAM arrays are not initialized out of any type of reset.
With the exception of resets resulting from low voltage conditions, the RAM content is unaltered by a reset
occurrence.
Vector base + 0x64
RTC
I bit
RTCCTL4(HRIE,MINIE,SECI
E,COMPIE,TB0IE)
Yes
Yes
Vector base + 0x60
SSG0 Ready For Next Data(RNDI)
I bit
SSG0IE(RNDIE)
No
Yes
Vector base + 0x5C
to
Vector base + 0x10
Reserved
1. 15 bits vector address based
Table 1-11. Interrupt Vector Locations (Sheet 4 of 4)
Vector Address
(1)
Interrupt Source
CCR
Mask
Local Enable
Wake up
from STOP
Wake up
from WAIT
