Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
145
Figure 5-1. BDC Block Diagram
5.2
External Signal Description
A single-wire interface pin (BKGD) is used to communicate with the BDC system. During reset, this pin
is a device mode select input. After reset, this pin becomes the dedicated serial interface pin for the BDC.
BKGD is a pseudo-open-drain pin with an on-chip pull-up. Unlike typical open-drain pins, the external
RC time constant on this pin due to external capacitance, plays almost no role in signal rise time. The
custom protocol provides for brief, actively driven speed-up pulses to force rapid rise times on this pin
without risking harmful drive level conflicts. Refer to
for more details.
5.3
Memory Map and Register Definition
5.3.1
Module Memory Map
shows the BDC memory map.
Table 5-4. BDC Memory Map
Global Address
Module
Size
(Bytes)
Not Applicable
BDC registers
2
BKGD
HOST
SYSTEM
SERIAL INTERFACE CONTROL
INSTRUCTION
DECODE AND
BUS INTERFACE
AND
CONTROL LOGIC
ADDRESS
DATA
BUS CONTROL
BDCSI
CORE CLOCK
ERASE FLASH
FLASH ERASED
CPU CONTROL
AND SHIFT REGISTER
FLASH SECURE
BDCCSR REGISTER
AND DATAPATH
CONTROL
CLOCK DOMAIN
CONTROL
FSM
