Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
Freescale Semiconductor
251
7.3.2.8
S12CPMU_UHV_V5 PLL Control Register (CPMUPLL)
This register controls the PLL functionality.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write
has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
NOTE
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
Module Base + 0x000A
7
6
5
4
3
2
1
0
R
0
0
FM1
FM0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
Figure 7-11. S12CPMU_UHV_V5 PLL Control Register (CPMUPLL)
Table 7-9. CPMUPLL Field Descriptions
Field
Description
5, 4
FM1, FM0
PLL
Frequency Modulation Enable Bits
— FM1 and FM0 enable frequency modulation on the VCOCLK. This
is to reduce noise emission. The modulation frequency is f
ref
divided by 16. See
for coding.
Table 7-10. FM Amplitude selection
FM1
FM0
FM Amplitude /
f
VCO
Variation
0
0
FM off
0
1
1%
1
0
2%
1
1
4%
