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Freescale Semiconductor MC9S12ZVHL32, Reference Manual

The Freescale Semiconductor MC9S12ZVHL32 is a powerful microcontroller designed for automotive applications. For a comprehensive understanding of its features and functionalities, make sure to download the free Reference Manual from manualshive.com. This manual provides detailed instructions for maximizing the performance of this cutting-edge product.

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Chapter 8 Timer Module (TIM16B8CV3) Block Description

S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 

Freescale Semiconductor 

    

307

Note: To enable output action using the OM7 and OL7 bits on the timer port,the corresponding bit OC7M7 
in the OC7M register must also be cleared. The settings for these bits can be seen in

Table 8-10

.

Note: in 

Table 8-10

, the IOS7 and IOSx should be set to 1

IOSx is the register TIOS bit x,

OC7Mx is the register OC7M bit x,

TCx is timer Input Capture/Output Compare register,

IOCx is channel x,

OMx/OLx is the register TCTL1/TCTL2,

OC7Dx is the register OC7D bit x.

IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value. 

8.3.2.9

Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)

Read: Anytime

Table 8-10. The OC7 and OCx event priority 

OC7M7=0

OC7M7=1

OC7Mx=1

OC7Mx=0

OC7Mx=1

OC7Mx=0

TC7=TCx

TC7>TCx

TC7=TCx

TC7>TCx

TC7=TCx

TC7>TCx

TC7=TCx

TC7>TCx

IOCx=OC7Dx
IOC7=OM7/O

L7

IOCx=OC7Dx

+OMx/OLx

IOC7=OM7/O

L7

IOCx=OMx/OLx

IOC7=OM7/OL7

IOCx=OC7Dx

IOC7=OC7D7

IOCx=OC7Dx

+OMx/OLx

IOC7=OC7D7

IOCx=OMx/OLx

IOC7=OC7D7

Module Base + 0x000A

 

7

6

5

4

3

2

1

0

R

EDG7B

EDG7A

EDG6B

EDG6A

EDG5B

EDG5A

EDG4B

EDG4A

W

Reset

0

0

0

0

0

0

0

0

Figure 8-16. Timer Control Register 3 (TCTL3)

Module Base + 0x000B

 

7

6

5

4

3

2

1

0

R

EDG3B

EDG3A

EDG2B

EDG2A

EDG1B

EDG1A

EDG0B

EDG0A

W

Reset

0

0

0

0

0

0

0

0

Figure 8-17. Timer Control Register 4 (TCTL4)

Summary of Contents for MC9S12ZVHL32

Page 1: ...S12 MagniV Microcontrollers freescale com MC9S12ZVHY MC9S12ZVHL Families Reference Manual MC9S12ZVHYRMV1 Rev 1 05 6 2015...

Page 2: ...n where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Se...

Page 3: ...river LCD 30 1 5 12 LIN physical layer transceiver 30 1 5 13 Stepper Motor Controller MC 31 1 5 14 Stepper Stall Detect SSD 31 1 5 15 Multi Scalable Controller Area Network MSCAN 31 1 5 16 Inter IC Bu...

Page 4: ...18 FTMRZ Connectivity 69 1 19 RTC Clock Source 69 1 20 LCD Clock Source Connectivity 70 1 21 32K OSC enable control 70 Chapter 2 Port Integration Module S12ZVHYPIMV1 2 1 Introduction 71 2 1 1 Overview...

Page 5: ...29 4 1 4 Block Diagram 129 4 2 External Signal Description 130 4 3 Memory Map and Register Definition 130 4 3 1 Module Memory Map 130 4 3 2 Register Descriptions 131 4 4 Functional Description 135 4 4...

Page 6: ...5 Application Information 178 5 5 1 Clock Frequency Considerations 178 Chapter 6 S12Z Debug S12ZDBGV2 Module 6 1 Introduction 179 6 1 1 Glossary 179 6 1 2 Overview 180 6 1 3 Features 180 6 1 4 Modes o...

Page 7: ...e 238 7 3 Memory Map and Registers 239 7 3 1 Module Memory Map 239 7 3 2 Register Descriptions 241 7 4 Functional Description 279 7 4 1 Phase Locked Loop with Internal Filter PLL 279 7 4 2 Startup fro...

Page 8: ...Output Compare 318 8 4 4 Pulse Accumulator 319 8 4 5 Event Counter Mode 320 8 4 6 Gated Time Accumulation Mode 320 8 5 Resets 320 8 6 Interrupts 320 8 6 1 Channel 7 0 Interrupt C 7 0 F 321 8 6 2 Pulse...

Page 9: ...10 8 1 List Usage CSL single buffer mode and RVL single buffer mode 412 10 8 2 List Usage CSL single buffer mode and RVL double buffer mode 412 10 8 3 List Usage CSL double buffer mode and RVL double...

Page 10: ...n Interface S12SCIV6 12 1 Introduction 475 12 1 1 Glossary 475 12 1 2 Features 476 12 1 3 Modes of Operation 477 12 1 4 Block Diagram 477 12 2 External Signal Description 478 12 2 1 TXD Transmit Pin 4...

Page 11: ...4 2 Slave Mode 529 13 4 3 Transmission Formats 530 13 4 4 SPI Baud Rate Generation 535 13 4 5 Special Features 536 13 4 6 Error Conditions 537 13 4 7 Low Power Mode Options 538 Chapter 14 Inter Integ...

Page 12: ...CD Waveform Examples 584 15 4 5 LCD Clock Inputs Reset Behavior 590 15 5 Resets 591 15 6 Interrupts 591 Chapter 16 Motor Controller MC10B8CV1 16 1 Introduction 593 16 1 1 Features 593 16 1 2 Modes of...

Page 13: ...ull Step States 632 17 4 3 Operation in Low Power Modes 636 17 4 4 Stall Detection Flow 636 Chapter 18 Real Time Counter With Calendar RTCV2 18 1 Introduction 639 18 2 Features 639 18 2 1 Modes of Ope...

Page 14: ...Signal Description 656 19 2 1 SGT 656 19 2 2 SGA 657 19 3 Memory Map and Register Definition 657 19 3 1 Module Memory Map 657 19 3 2 Register Descriptions 657 19 4 Functional Description 668 19 4 1 SS...

Page 15: ...Operations 716 21 4 6 Allowed Simultaneous P Flash and EEPROM Operations 721 21 4 7 Flash Command Description 722 21 4 8 Interrupts 738 21 4 9 Wait Mode 738 21 4 10Stop Mode 739 21 5 Security 739 21...

Page 16: ...Descriptions 758 23 4 Functional Description 765 23 4 1 General 765 23 4 2 Slew Rate and LIN Mode Selection 765 23 4 3 Modes 766 23 4 4 Interrupts 769 23 5 Application Information 772 23 5 1 Module In...

Page 17: ...ecifications F 1 MSCAN Electrical Characteristics 801 Appendix G NVM Electrical Parameters G 1 NVM Timing Parameters 803 G 2 NVM Reliability Parameters 804 Appendix H BATS Electrical Specifications H...

Page 18: ...Slave Mode 819 Appendix M LIN HV PHY Electrical Specifications M 1 Maximum Ratings 823 M 2 Static Electrical Characteristics 823 M 3 Dynamic Electrical Characteristics 824 Appendix N Ordering Informa...

Page 19: ...Chapter 12 Serial Communication Interface S12SCIV6 475 Chapter 13 Serial Peripheral Interface S12SPIV5 515 Chapter 14 Inter Integrated Circuit IICV3 Block Description 541 Chapter 15 Liquid Crystal Dis...

Page 20: ...ecifications 807 Appendix I VREG Electrical Specifications 811 Appendix J Electrical Characteristics for the Oscillator OSCLCPcr 813 Appendix K OSC32K Electrical Specifications 815 Appendix L SPI Elec...

Page 21: ...S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 21 PAGE INTENTIONALLY LEFT BLANK...

Page 22: ...S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 22 Freescale Semiconductor PAGE INTENTIONALLY LEFT BLANK...

Page 23: ...please contact Freescale sales office for detailed information on software SSD The MC9S12ZVHY MC9S12ZVHL Families deliver an optimized solution with the integration of several key system components in...

Page 24: ...ins LQFP 100 pins LQFP 144 pins LQFP CPU HCS12Z HCS12Z Flash memory ECC 64 KB 32 KB EEPROM ECC 2 KB 2KB RAM ECC 4 KB 2 KB Stepper Motor Drive with HW SSD 2 2 Segment LCD 4 x 32 4 x 40 4 x 32 4 x 40 Si...

Page 25: ...nt clock source 1 with independent clock source Key Wakeup I Os 19 24 19 24 General purpose I Os 5 V 1 up to 73 for ZVHY up to 78 for ZVHL up to 100 up to 73 for ZVHY up to 78 for ZVHL up to 100 Direc...

Page 26: ...grated Circuit IIC module One Serial Peripheral Interface SPI module Two Serial Communication Interface SCI module supporting LIN 1 3 2 0 2 1 and SAE J2602 communications on ZVHY One serial communicat...

Page 27: ...ach configurable to monitor PC addresses or addresses of data accesses A and C compare full address bus and full 32 bit data bus with data bus mask register B and D compare full address bus only Three...

Page 28: ...mode with the entire device clocked WAIT mode when the internal CPU clock is switched off so the CPU does not execute instructions Pseudo STOP system clocks are stopped but the RTI COP API RTC and LC...

Page 29: ...in for typical crystals Oscillator pins shared with GPIO functionality 1 5 5 32K External Oscillator Low speed oscillator using 32 kHz to 40 kHz crystal Low power Good noise immunity Oscillator pins s...

Page 30: ...ect logic with a wide range of frequencies 1 5 10 Simple Sound Generator SSG Programmable amplitude level with maximum 11 bit resolution from zero amplitude to max amplitude Sound STOP function to sto...

Page 31: ...or 1N39G 1 5 13 Stepper Motor Controller MC PWM motor controller MC with up to 16 high current outputs Each PWM channel switchable between two drivers in an H bridge configuration Left right and cente...

Page 32: ...ion detection Bus busy detection General Call Address detection Compliant to ten bit address 1 5 17 Serial Communication Interface Module SCI Full duplex or single wire operation Standard mark space n...

Page 33: ...igital I O 1 5 20 Supply Voltage Sensor BATS VSENSE VSUP pin low or a high voltage interrupt VSENSE VSUP pin can be routed via an internal divider to the internal ADC channel Generation of low or high...

Page 34: ...IRQ function PWM0 PWM 7 0 SCI0 Asynchronous Serial IF SS0 SCK0 MOSI0 MISO0 SPI0 Synchronous Serial IF 40 X 4 LCD display PU 7 0 PTAD KWAD SSG0 SGA0 SGT0 Up to 4 KB RAM with ECC Up to 2 KB EEPROM with...

Page 35: ...FF MMC 144 0x0100 0x017F DBG 128 0x0180 0x01FF Reserved 128 0x0200 0x037F PIM 384 0x0380 0x039F FTMRZ 32 0x03A0 0x03BF Reserved 32 0x03C0 0x03CF RAM ECC 16 0x03D0 0x03FF Reserved 48 0x0400 0x042F TIM1...

Page 36: ...locations returns zero 0x0788 0x07BF Reserved 56 0x07C0 0x07C7 IIC0 8 0x07C8 0x07FF Reserved 56 0x0800 0x083F CAN0 64 0x0840 0x097F Reserved 320 0x0980 0x0987 LINPHY 8 0x0988 0x09FF Reserved 120 0x0A...

Page 37: ...MC9S12ZVHL Families Global Memory Map 0x00_1000 0x00_0000 0x10_0000 0x1F_4000 0x80_0000 0xFF_FFFF RAM EEPROM Unimplemented Program NVM Register Space 4 KB max 1 MB 4 KB max 1 MB 48 KB max 8 MB 6 MB Hi...

Page 38: ...l IP blocks on the device 1 7 1 Pin Assignment Overview Table 1 6 provides a summary of which ports are available for 100 pin and 144 pin package option Table 1 5 Assigned IDs Numbers Device Mask Set...

Page 39: ...pull down device NOTE The TEST pin must be tied to ground in all applications 1 7 2 3 MODC Mode C Signal The MODC signal is used as a MCU operating mode select during reset The state of this signal is...

Page 40: ...basis Out of reset the pull down devices are enabled 1 7 2 9 PE 3 0 Port E I O Signals PE 3 0 are general purpose input or output signals They can have a pull up or pull down device selected and enab...

Page 41: ...bility KWT 7 0 These signals can have a pull up or pull down device selected and enabled on per signal basis Out of reset the pull devices are disabled 1 7 2 17 PU 7 0 Port U I O Signals PU 7 0 are ge...

Page 42: ...faces SCI 1 0 1 7 2 22 CAN0 Signals 1 7 2 22 1 RXCAN0 Signal This signal is associated with the receive functionality of the scalable controller area network controller MSCAN0 1 7 2 22 2 TXCAN0 Signal...

Page 43: ...1 7 2 27 2 SGA0 Signals The signal is from SSG0 output it contain the amplitude digital output 1 7 2 28 IIC0 Signals 1 7 2 28 1 SDA0 Signal This signal is associated with the serial data pin of IIC0 1...

Page 44: ...rence clock EXTAL is the oscillator input XTAL is the oscillator output 1 7 2 32 2 32 768kHz Oscillator Pins 32K_EXTAL and 32K_XTAL 32K_EXTAL and 32K_XTAL are the 32 768KHZ crystal driver On reset the...

Page 45: ...ut only and provides a serial encoded data stream that can be used by external development tools to reconstruct the internal CPUcode flow 1 7 2 33 3 PDOCLK Profiling Data Output Clock This is the PDO...

Page 46: ...e high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible NOTE All ground pins must be connecte...

Page 47: ...ominally 1 8V is generated by the internal voltage regulator The return current path is through the VSS1 and VSS2 pin 1 7 5 6 VSUP Voltage Supply Pin for Voltage Regulator VSUP is the 12V supply volta...

Page 48: ...FP21 PF5 FP20 PF4 FP19 PF3 FP18 PF2 BKGD MODC PC7 TXD1 PC6 RXD1 PC5 SGA0 IOC0_7 PC4 SGT0 IOC0_6 PT4 PDO IOC1_4 KWT4 PT3 PDOCLK IOC1_3 KWT3 PT2 DBGEEV IOC1_2 KWT2 PT1 RTC_CAL IOC1_1 KWT1 PT0 API_EXTCLK...

Page 49: ...VSS3 NC KWT6 IOC1_6 ECLK PT6 FP22 PF6 FP21 PF5 FP20 PF4 FP19 PF3 FP18 PF2 BKGD MODC PC5 SGA0 IOC0_7 PC4 SGT0 IOC0_6 PT4 PDO IOC1_4 KWT4 PT3 PDOCLK IOC1_3 KWT3 PT2 DBGEEV IOC1_2 KWT2 PT1 RTC_CAL IOC1_1...

Page 50: ...0M IOC0_2 PU4 M1COSP M1C0P PU5 M1SINM M1C1M IOC0_3 PU6 M1SINP M1C1P PU7 LGND LIN KWT6 IOC1_6 ECLK PT6 FP22 PF6 FP21 PF5 FP20 PF4 FP19 PF3 FP18 PF2 BKGD MODC PC5 SGA0 IOC0_7 PC4 SGT0 IOC0_6 PT4 PDO IOC...

Page 51: ...isabled 10 9 PU1 M0C0P M0COSP VDDM PERU PPSU Disabled 11 10 PU2 IOC0_1 M0C1M M0SINM VDDM PERU PPSU Disabled 12 11 PU3 M0C1P M0SINP VDDM PERU PPSU Disabled 13 12 VDDM1 14 13 VSSM1 VDDM 15 14 PU4 IOC0_2...

Page 52: ...PPSF Pull Down 35 24 PF3 FP19 VDDX PERF PPSF Pull Down 36 25 PF2 FP18 VDDX PERF PPSF Pull Down 37 26 PF1 FP17 VDDX PERF PPSF Pull Down 38 27 PF0 FP16 VDDX PERF PPSF Pull Down 39 28 PD7 FP15 VDDX PERD...

Page 53: ...6 PA4 PWM0 FP4 VDDX PERA PPSA Pull Down 51 37 PA3 SDA0 FP3 VDDX PERA PPSA Pull Down 52 38 PA2 SCL0 FP2 VDDX PERA PPSA Pull Down 53 PA1 FP1 VDDX PERA PPSA Pull Down 54 PA0 FP0 VDDX PERA PPSA Pull Down...

Page 54: ...0 EXTAL VDDX PERE PPSE Pull Down 68 48 PE1 XTAL VDDX PERE PPSE Pull Down 69 49 VSSX1 70 50 VDDX1 VDDX 71 PP6 PWM6 VDDX PERP PPSP Disabled 72 PT5 IOC1_5 KWT5 VDDX PERT PPST Disabled 73 51 VSUP VSUP 74...

Page 55: ...PERS PPSS Pull Up 95 64 PS6 RXD0 XIRQ KWS6 VDDX PERS PPSS Pull Up 96 65 PS7 TXD0 LPDC0 3 IRQ KWS7 VDDX PERS PPSS Pull Up 97 66 VDDX2 VDDX 98 67 VSSX2 99 68 PT0 API_EXT CLK IOC1_0 KWT0 VDDX PERT PPST...

Page 56: ...PER1AD PPS1AD Disabled 112 79 PAD3 AN0_3 KWAD3 VDDA PER1AD PPS1AD Disabled 113 PAD4 AN0_4 KWAD4 VDDA PER1AD PPS1AD Disabled 114 PAD5 AN0_5 KWAD5 VDDA PER1AD PPS1AD Disabled 115 PAD6 AN0_6 KWAD6 VDDA P...

Page 57: ...3 132 PH7 FP39 VDDX PERH PPSH Pull Down 133 PH6 FP38 VDDX PERH PPSH Pull Down 134 PH5 FP37 VDDX PERH PPSH Pull Down 135 92 PH4 FP36 VDDX PERH PPSH Pull Down 136 93 PH3 FP35 VDDX PERH PPSH Pull Down 13...

Page 58: ...mode out of reset is determined by the state of the MODC signal during reset Table 1 8 The MODC bit in the MODE register shows the current operating mode and provides limited mode switching during ope...

Page 59: ...power mode Run Run mode is the main full performance operating mode with the entire device clocked The user can configure the device operating speed through selection of the clock source and the phase...

Page 60: ...n this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state In this example the security of the application could be e...

Page 61: ...ash block description In special single chip mode the device is in active BDM after reset In special single chip mode on a secure device only the BDC mass erase and BDC control and status register com...

Page 62: ...r key and the interrupt vectors will also be erased this method is not recommended for normal single chip mode The application software can only erase and program the Flash options security byte if th...

Page 63: ...base 0x1F4 Unimplemented page2 op code trap TRAP None None Vector base 0x1F0 Software interrupt instruction SWI None None Vector base 0x1EC System call interrupt instruction SYS None None Vector base...

Page 64: ...0x180 Oscillator status interrupt I bit CPMUINT OSCIE No Yes Vector base 0x17C PLL lock interrupt I bit CPMUINT LOCKIE No Yes Vector base 0x178 to Vector base 0x174 Reserved Vector base 0x170 RAM erro...

Page 65: ...timer channel 1 I bit TIM1TIE C1I No Yes Vector base 0xA4 TIM1 timer channel 2 I bit TIM1TIE C2I No Yes Vector base 0xA0 TIM1 timer channel 3 I bit TIM1TIE C3I No Yes Vector base 0x9C TIM1 timer chan...

Page 66: ...lash Command Active If a reset occurs while any Flash command is in progress that command will be immediately aborted The state of the word being programmed or the sector block being erased is not gua...

Page 67: ...ld byte at global address 0xFF_FE0E during the reset sequence See Table 1 12 and Table 1 13 for coding 1 13 ADC0 Internal Channels Table 1 14 lists the internal sources which are connected to these sp...

Page 68: ...rnal reference voltage VBG see Table 1 14 VBG is a constant voltage with a narrow distribution over temperature and external voltage supply see Table A 16 A 10 bit right justified1 ADC conversion resu...

Page 69: ...c_erase_all_req input to the flash module is driven directly by a BDC erase flash request resulting from the BDC ERASE_FLASH command The FTMRZ FCLKDIV register is forced to 0x05 by the BDC ERASE_FLASH...

Page 70: ...Section 18 4 2 RTC Control Register 2 RTCCTL2 to get the expect RTCCLK frequency if it uses the main OSC as clock source 1 21 32K OSC enable control The 32K OSC enable is controlled by the RTCCTL2 CLK...

Page 71: ...and rerouting of IIC 4 pin port B associated with the LCD BP 3 0 8 pin port C associated with TIM0_IOC 7 4 MSCAN0 SCI1 SSG0 and LINPHY0 s LPTXD0 LPRXD0 8 pin port D associated with LCD FP 15 8 4 pin p...

Page 72: ...C Guide 2 1 2 Features The PIM includes these distinctive registers Data registers and data direction registers for ports A B C D E F G H T S P AD U and J when used as general purpose I O Control regi...

Page 73: ...l on motor pads 2 2 External Signal Description This section lists and describes the signals that do connect off chip Table 2 1 shows all pins with the pins and functions that are controlled by the PI...

Page 74: ...WM6RR PTA 4 I O General purpose PA3 FP3 O LCD FP3 signal SDA0 I O SDA of IIC0 signal IIC0RR PTA 3 I O General purpose PA2 FP2 O LCD FP2 signal SCL0 I O SCL of IIC0 signal IIC0RR PTA 2 I O General purp...

Page 75: ...XD0 O RXD of LINPHY0 S0L00RR2 0 PTC 2 I O General purpose PC1 TXCAN0 O TX of MSCAN0 C0RR PTC 1 I O General purpose PC0 RXCAN0 I RX of MSCAN0 C0RR PTC 0 I O General purpose D PD7 FP15 O LCD FP15 signal...

Page 76: ...purpose F PF7 FP23 O LCD FP23 signal GPIO PTF 7 I O General purpose PF6 FP22 O LCD FP22 signal PTF 6 I O General purpose PF5 FP21 O LCD FP21 signal PTF 5 I O General purpose PF4 FP20 O LCD FP20 signal...

Page 77: ...FP24 O LCD FP24 signal PTG 0 I O General purpose H PH7 FP39 O LCD FP39 signal GPIO PTH 7 I O General purpose PH6 FP38 O LCD FP38 signal PTH 6 I O General purpose PH5 FP37 O LCD FP37 signal PTH 5 I O...

Page 78: ...General purpose PP5 RXD1 O RXD of SCI1 SCI1RR PWM5 O PWM channel 5 PP 5 I O General purpose PP4 PWM4 O PWM channel 4 PP 4 I O General purpose PP3 PWM3 O PWM channel 3 PP 3 I O General purpose PP2 PWM...

Page 79: ...IC0 TXCAN0 I O TX of MSCAN0 C0RR PTS 5 KWS 5 I O General purpose with interrupt and wakeup PS4 SCL0 O SCL of IIC0 RXCAN I O RX of MSCAN0 C0RR PTS 4 KWS 4 I O General purpose with interrupt and wakeup...

Page 80: ...data output PTT 4 KWT 4 I O General purpose with interrupt and wakeup PT3 IOC1_3 I O TIM1 channel 3 PDOCLK O DBG profiling clock PTT 3 KWT 3 I O General purpose with interrupt and wakeup PT2 IOC1_2 I...

Page 81: ...h interrupt and wakeup PAD4 AN0_4 I ADC0 analog input 4 PTADL 4 KWADL 4 I O General purpose with interrupt and wakeup PAD3 AN0_3 I ADC0 analog input 3 PTADL 3 KWADL 3 I O General purpose with interrup...

Page 82: ...3 M0SINP I O SSD0 Sine Node M0C1P O Motor control output for motor 0 PTU 3 I O General purpose PU 2 M0SINM I O SSD0 Sine Node M0C1M O Motor control output for motor 0 IOC0_1 I O TIM0 channel 1 PTU 2...

Page 83: ...0x0204 0x0207 Reserved R 0 0 0 0 0 0 0 0 W 0x0208 ECLKCTL R NECLK 0 0 0 0 0 0 0 W 0x0209 IRQCR R IRQE IRQEN 0 0 0 0 0 0 W 0x020A PIMMISC R 0 0 0 0 0 0 0 CALCLKE N W 0x020B 0x020D Reserved R 0 0 0 0 0...

Page 84: ...PSA5 PPSA4 PPSA3 PPSA2 PPSA1 PPSA0 W 0x0229 PPSB R 0 0 0 0 PPSB3 PPSB2 PPSB1 PPSB0 W 0x022A 0x023D Reserved R 0 0 0 0 0 0 0 0 W 0x023E WOMA R 0 0 0 0 WOMA3 WOMA2 0 0 W 0x023F Reserved R 0 0 0 0 0 0 0...

Page 85: ...R 0 0 0 0 PTE3 PTE2 PTE1 PTE0 W 0x0261 PTF R PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 W 0x0262 PTIE R 0 0 0 0 PTIE3 PTIE2 PTIE1 PTIE0 W 0x0263 PTIF R PTIF7 PTIF6 PTIF5 PTIF4 PTIF3 PTIF2 PTIF1 PTIF0 W...

Page 86: ...L3 DDRADL2 DDRADL1 DDRADL0 W 0x0286 Reserved R 0 0 0 0 0 0 0 0 W 0x0287 PERADL R PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 PERADL2 PERADL1 PERADL0 W 0x0288 Reserved R 0 0 0 0 0 0 0 0 W 0x0289 PPSADL R P...

Page 87: ...T5 PERT4 PERT3 PERT2 PERT1 PERT0 W 0x02C4 PPST R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W 0x02C5 Reserved R 0 0 0 0 0 0 0 0 W 0x02C6 PIET R PIET7 PIET6 PIET5 PIET4 PIET3 PIET2 PIET1 PIET0 W 0...

Page 88: ...TP R PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W 0x02F1 PTIP R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 W 0x02F2 DDRP R DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 W 0x02F3 PERP R PERP7 PERP6...

Page 89: ...0x0314 PPSJ R 0 0 0 0 PPSJ3 PPSJ2 PPSJ1 PPSJ0 W 0x0315 0x031F Reserved R 0 0 0 0 0 0 0 0 W 0x0320 PTG R PTG7 PTG6 PTG5 PTG4 PTG3 PTG2 PTG1 PTG0 W 0x0321 PTIG R PTIG7 PTIG6 PTIG5 PTIG4 PTIG3 PTIG2 PTIG...

Page 90: ...lways reflect the pin status independent of the use Pull device availability pull device polarity wired or mode key wake up functionality are independent of the prioritization unless noted differently...

Page 91: ...e Routing Register0 Field Descriptions Field Description 3 C0RR Module Routing Register CAN0 routing 1 TXCAN0 on PS5 and RXCAN0 on PS4 0 TXCAN0 on PC1 and RXCAN0 on PC0 Address 0x0201 Access User read...

Page 92: ...1 IC0 Reset 0 0 0 0 0 0 0 0 Figure 2 3 Module Routing Register 2 MODRR2 Table 2 4 MODRR2 Routing Register Field Descriptions Field Description 5 SCI1RR Module Routing Register SCI1 routing 1 TXD1 on P...

Page 93: ...3 2 1 0 R 0 0 0 0 0 S0L0RR2 0 W SCI0 LINPHY0 see Figure 2 5 Reset 0 0 0 0 0 0 0 0 Figure 2 4 Module Routing Register 3 MODRR3 Field Description 2 0 S0L0RR2 0 Module Routing Register SCI0 LINPHY0 rout...

Page 94: ...LINPHY0 interface internal only 001 LPDR1 LPTXD0 LPRXD RXD0 Direct control setting LP0DR LPDR1 register bit controls LPTXD0 interface internal only 100 TXD0 LPTXD0 PS7 LPRXD0 RXD0 PC2 Probe setting S...

Page 95: ...er IRQCR Address 0x0208 Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R NECLK 0 0 0 0 0 0 0 W Reset 1 0 0 0 0 0 0 0 Figure 2 6 ECLK Control Register ECLKCTL Table 2 6 ECLKCTL R...

Page 96: ...ed only upon a reset or the servicing of the IRQ interrupt 0 IRQ configured for low level recognition 6 IRQEN IRQ enable 1 IRQ pin is connected to interrupt logic 0 IRQ pin is disconnected from interr...

Page 97: ...Reserved Reserved Reserved Reserved W Reset x x x x x x x x Figure 2 9 Reserved Register Address 0x020F Access User read write 1 1 Read Anytime Write Only in special mode These reserved registers are...

Page 98: ...vice selected 0 pullup device selected 0 PPSC Port C Pull Polarity Select Configure pull device on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin...

Page 99: ...in a pullup device can be activated on the RXCAN0 input attempting to select a pulldown disables the pull device 1 pulldown device selected rising edge selected 0 pullup device selected falling edge s...

Page 100: ...f these pins are set to 1 a read returns the value of the port register otherwise the buffered pin input state is read Address 0x0222 PTIA 0x0223 PTIB 0x0242 PTIC 0x0243 PTID 0x0262 PTIE 0x0263 PTIF 0...

Page 101: ...time the highest ranked module according the predefined priority scheme in Table 2 1 will take precedence on the pin Address 0x0224 DDRA 0x0225 DDRB 0x0244 DDRC 0x0245 DDRD 0x0264 DDRE 0x0265 DDRF 0x0...

Page 102: ...et 0 0 0 0 0 0 0 0 Figure 2 16 Digital Input Enable Register Table 2 14 Digital Input Enable Register Field Descriptions Field Description 7 0 DIENx Digital Input Enable Input buffer control This bit...

Page 103: ...PERx4 PERx3 PERx2 PERx1 PERx0 W Reset Ports B E 0 0 0 0 1 1 1 1 Ports C P T ADL J U 0 0 0 0 0 0 0 0 Others 1 1 1 1 1 1 1 1 Figure 2 17 Pull Device Enable Register Table 2 15 Pull Device Register Fiel...

Page 104: ...0 1 1 1 1 Ports A D F G H 1 1 1 1 1 1 1 1 Others 0 0 0 0 0 0 0 0 Figure 2 18 Polarity Select Register Table 2 16 Polarity Select Register Field Descriptions Field Description 7 0 PPSx Pull Polarity Se...

Page 105: ...tion of several serial modules These bits have no influence on pins used as inputs Enable the IIC0 it will force the corresponding pins to be open drain output 1 Output buffers operate as open drain o...

Page 106: ...the related pin see Section 2 4 4 Pin interrupts and Wakeup This can be a rising or a falling edge based on the state of the polarity select register Writing a logic 1 to the corresponding bit field...

Page 107: ...nanoseconds delay before the slew rate control to be real function as setting When enter STOP to save the power the slew rate control will be force to off state After wakeup from STOP it will also nee...

Page 108: ...Forced output Forced off ICx None DDR maintains control None PER PPS maintain control SPIx MISO MOSI SCK SS Controlled input output Forced off if output SCIx TXD Forced output Forced off RXD Forced i...

Page 109: ...only and always returns the synchronized state of the pin Figure 2 24 2 4 2 3 Data direction register DDRx This register defines whether the pin is used as an general purpose input or an output If a p...

Page 110: ...to the respective bit descriptions 2 4 2 5 Polarity select register PPSx This register selects either a pullup or pulldown device if enabled It becomes only active if the pin is used as an input A pu...

Page 111: ...IM1IC0 IIC0 and SCI1 rerouting MODRR3 supports LINPHY0 and SCI0 rerouting 2 4 3 Interrupts This section describes the interrupts generated by the PIM and their individual sources Vector addresses and...

Page 112: ...on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level Else the sampling logic is restarted In run and wait mode the filters are c...

Page 113: ...ure TIM1 IC0 to measure time between incoming signal edges 2 5 3 RTC on chip calibration The on chip RTC calibration used the TIM1 IC0 and IC1 channel 1 Establish the link Set the RTC configuration to...

Page 114: ...Chapter 2 Port Integration Module S12ZVHYPIMV1 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 114 Freescale Semiconductor...

Page 115: ...n chip resources regulates access priorities and enforces memory protection Figure 3 1 shows a block diagram of the S12ZMMC module Revision Number Revision Date Sections Affected Description of Change...

Page 116: ...hine exceptions upon detection of illegal memory accesses and uncorrectable ECC errors Logs the state of the S12ZCPU and the cause of the access error 3 1 4 Modes of Operation 3 1 4 1 Chip configurati...

Page 117: ...iew for the mapping of these signals to device pins 3 3 Memory Map and Register Definition 3 3 1 Memory Map A summary of the registers associated with the MMC block is shown in Figure 3 2 Detailed des...

Page 118: ...4 3 2 1 Bit 0 0x0070 MODE R MODC 0 0 0 0 0 0 0 W 0x0071 0x007F Reserved R 0 0 0 0 0 0 0 0 W 0x0080 MMCECH R ITR 3 0 TGT 3 0 W 0x0081 MMCECL R ACC 3 0 ERR 3 0 W 0x0082 MMCCCRH R CPUU 0 0 0 0 0 0 0 W 0x...

Page 119: ...eset MODC1 0 0 0 0 0 0 0 1 External signal see Table 3 3 Unimplemented or Reserved Figure 3 3 Mode Register MODE Table 3 4 MODE Field Descriptions Field Description 7 MODC Mode Select Bit This bit det...

Page 120: ...0 0 Address 0x0081 MMCECL 7 6 5 4 3 2 1 0 R ACC 3 0 ERR 3 0 W Reset 0 0 0 0 0 0 0 0 Field Description 7 4 MMCECH ITR 3 0 Initiator Field The ITR 3 0 bits capture the initiator which caused the access...

Page 121: ...ure 3 6 Captured S12ZCPU Condition Code Register MMCCCRH MMCCCRL Read Anytime Write Never 7 4 MMCECL ACC 3 0 Access Type Field The ACC 3 0 bits capture the type of memory access which caused the acces...

Page 122: ...X Interrupt Mask This bit shows the state of the X interrupt mask in the S12ZCPU s CCR at the time the access violation has occurred The S12ZCPU X interrupt mask is read only it will be automatically...

Page 123: ...n chip resources into an 16MB address space the global memory map The exact resource mapping is shown in Figure 3 8 The global address space is used by the S12ZCPU ADC and the S12ZBDC module Field Des...

Page 124: ...al Memory Map 0x00_1000 0x00_0000 0x10_0000 0x1F_4000 0x80_0000 0xFF_FFFF RAM EEPROM Unmapped Program NVM Register Space 4 KB max 1 MByte 4 KB max 1 MByte 48 KB max 8 MByte 6 MByte High address aligne...

Page 125: ...ok Code execution ok EEPROM Read access ok 1 1 Unsupported NVM accesses during NVM command execution collisions are treated as illegal accesses ok1 ok1 Write access illegal access illegal access illeg...

Page 126: ...ot be executed in the program flow To avoid these machine exceptions S12ZCPU instructions must not be executed from the last high addresses 8 bytes of RAM EEPROM and Flash 3 4 3 Uncorrectable ECC Faul...

Page 127: ...Replaced mentions of CCR old name from S12X with CCW new name V00 05 12 Jan 2011 all Corrected wrong IRQ vector address in some descriptions V00 06 22 Mar 2011 all Added vectors for RAM ECC and NVM E...

Page 128: ...ector at address vector base1 0x0001F8 One non maskable unimplemented page2 op code trap TRAP vector at address vector base1 0x0001F4 One non maskable software interrupt request SWI vector at address...

Page 129: ...rity levels Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or whenever XIRQ is asserted even if X interrupt is masked 4 1 3 Modes of Operation Run mode This is...

Page 130: ...se Access 0x000010 0x000011 Interrupt Vector Base Register IVBR R W 0x000012 0x000016 RESERVED 0x000017 Interrupt Request Configuration Address Register INT_CFADDR R W 0x000018 Interrupt Request Confi...

Page 131: ...INT_CFDATA4 R W 0x00001D Interrupt Request Configuration Data Register 5 INT_CFDATA5 R W 0x00001E Interrupt Request Configuration Data Register 6 INT_CFDATA6 R W 0x00001F Interrupt Request Configurati...

Page 132: ...le 4 4 IVBR Field Descriptions Field Description 15 1 IVB_ADDR 15 1 Interrupt Vector Base Address Bits These bits represent the upper 15 bits of all vector addresses Out of reset these bits are set to...

Page 133: ...window at INT_CFDATA0 7 The hexadecimal value written to this register corresponds to the upper 4 bits of the vector number multiply with 4 to get the vector address offset If for example the value 0x...

Page 134: ...t 0 0 0 0 0 0 0 1 1 1 Please refer to the notes following the PRIOLVL 2 0 description below Unimplemented or Reserved Figure 4 9 Interrupt Request Configuration Data Register 4 INT_CFDATA4 Address 0x0...

Page 135: ...terrupt requests are enabled at the lowest active level 1 Please also refer to Table 4 7 for available interrupt request priority levels Note Write accesses to configuration data registers of unused i...

Page 136: ...t enabled bit in the peripheral module must be set 2 The setup in the configuration register associated with the interrupt request channel must meet the following conditions a The priority level must...

Page 137: ...est vector at address vector base 0x0001DC 4 4 4 Reset Exception Requests The INT module supports one system reset exception request The different reset types are mapped to this vector for details ple...

Page 138: ...sts Enable I bit maskable interrupts by clearing the I bit in the CCW Enable the X bit maskable interrupt by clearing the X bit in the CCW if required 4 5 2 Interrupt Nesting The interrupt request pri...

Page 139: ...ample 4 5 3 Wake Up from Stop or Wait Mode 4 5 3 1 CPU Wake Up from Stop or Wait Mode Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking the MCU f...

Page 140: ...errupt request i e care must be taken that the X bit maskable interrupt request used for wake up remains active at least until the system begins execution of the instruction following the WAI or STOP...

Page 141: ...ependency V2 06 22 Mar 2013 Section 5 3 2 2 Improved NORESP description of STEP1 Wait mode dependency V2 07 11 Apr 2013 Section 5 1 3 3 1 Improved STOP and BACKGROUND interdepency description V2 08 31...

Page 142: ...3 1 BDC Modes The BDC features module specific modes namely disabled enabled and active These modes are dependent on the device security and operating mode In active BDM the CPU ceases execution to al...

Page 143: ...cycles If no other module delays stop mode entry and exit then these additional clock cycles represent a difference between the debug and not debug cases Furthermore if a BDC internal access is being...

Page 144: ...nds classified as Non Intrusive or Always Available are possible in wait mode On entering wait mode the WAIT flag in BDCCSR is set If the ACK handshake protocol is enabled then the first ACK generated...

Page 145: ...ue to external capacitance plays almost no role in signal rise time The custom protocol provides for brief actively driven speed up pulses to force rapid rise times on this pin without risking harmful...

Page 146: ...E_BDCCSR commands Bit 5 can only be written by WRITE_BDCCSR commands when the device is not in stop mode Bits 6 1 and 0 cannot be written They can only be updated by internal hardware Global Address R...

Page 147: ...ol enabled If ACK handshaking is disabled then BDC accesses steal the next bus cycle 0 If ACK is enabled then BDC accesses await a free cycle with a timeout of 512 cycles 1 If ACK is enabled then BDC...

Page 148: ...ll set forcing subsequent ACK pulses to be long Unimplemented BDC opcodes causing the ILLCMD bit to be set do not generate a long ACK because this could conflict with further transmission from the hos...

Page 149: ...If a BACKGROUND command is issued whilst the device is in wait mode the NORESP bit is set but the command is not aborted The active BDM request is completed when the device leaves wait mode Furthermo...

Page 150: ...for receiving the first command 10 core clock cycles after the deassertion of the internal reset signal This is delayed relative to the external pin reset as specified in the device reset documentati...

Page 151: ...C internal clock is named BDCSI clock If BDCSI clock is mapped to the BDCCLK by CLKSW then the serial interface communication is not affected by bus core clock frequency changes If the BDC is mapped t...

Page 152: ...t such accesses occur infrequently For data read commands the external host must wait at least 16 BDCSI clock cycles after sending the address before attempting to obtain the read data This is to be c...

Page 153: ...bits of read data in the target to host direction rd16 16 bits of read data in the target to host direction rd24 24 bits of read data in the target to host direction rd32 32 bits of read data in the...

Page 154: ...d Subsequent FILL_MEM commands write sequential operands FILL_MEM sz_WS Non Intrusive No 0x13 4 x sz wd sz d ss Fill write memory based on operand size sz and report status Used with WRITE_MEM _WS to...

Page 155: ...reads return content of same address READ_SAME sz_WS Non Intrusive No 0x51 4 x sz d ss rd sz Read from location An initial READ_MEM defines the address subsequent READ_SAME reads return content of sam...

Page 156: ...his speed error If the SYNC request is detected by the target any partially executed command is discarded This is referred to as a soft reset equivalent to a timeout in the serial communication After...

Page 157: ...o allow the target MCU to finish its current CPU instruction and enter active background mode before a new BDC command can be accepted The host debugger must set ENBDC before attempting to send the BA...

Page 158: ...urned before the read data This status byte reflects the state after the memory read was performed If enabled an ACK pulse is driven before the data bytes are transmitted The effect of the access size...

Page 159: ...altered The examples show the DUMP_MEM B _WS DUMP_MEM W _WS and DUMP_MEM L _WS commands 5 4 4 6 FILL_MEM sz FILL_MEM sz_WS FILL_MEM sz Write memory specified by debug address register then increment a...

Page 160: ...ext address to be accessed is explained in more detail in Section 5 4 5 2 NOTE FILL_MEM _WS is a valid command only when preceded by SYNC NOP WRITE_MEM _WS or another FILL_MEM _WS command Otherwise an...

Page 161: ...CK If a GO_UNTIL is not acknowledged then a SYNC command must be issued to end the pending GO_UNTIL If a GO_UNTIL command is issued whilst BDM is inactive an illegal command response is returned and t...

Page 162: ...MEM sz Read memory at the specified address Non intrusive 0x30 Address 23 0 Data 7 0 host target host target D A C K target host 0x34 Address 23 0 Data 15 8 Data 7 0 host target host target D A C K ta...

Page 163: ...ption for more detailed information If enabled an ACK pulse is generated before each 32 bit longword is ready to be read by the host After issuing the first ACK a timeout is still possible whilst acce...

Page 164: ...BDCCSR status register This command can be executed in any mode 5 4 4 15 SYNC_PC This command returns the 24 bit CPU PC value to the host Unsuccessful SYNC_PC accesses return 0xEE for each byte If en...

Page 165: ...y after the command If the with status option is specified the status byte contained in BDCCSRL is returned after the write data This status byte reflects the state after the memory write was performe...

Page 166: ...enerated after the internal write access has been completed or aborted If the device is not in active BDM this command is rejected as an illegal operation the ILLCMD bit is set and no operation is per...

Page 167: ...LASH can be aborted by a SYNC pulse forcing a soft reset NOTE Device Bus Frequency Considerations The ERASE_FLASH command requires the default device bus clock frequency after reset Thus the bus clock...

Page 168: ...each byte After an illegal access FILL_MEM and READ_SAME commands are not valid and it is necessary to restart the internal access sequence with READ_MEM or WRITE_MEM An illegal access does not break...

Page 169: ...an attempted misaligned word access across a 4 byte boundary as shown in row 7 The following word access in row 8 continues from the realigned address of row 7 d Address 1 0 Access Size 00 01 10 11 N...

Page 170: ...CLKSW bit in the BDCCSR register This clock is referred to as the target clock in the following explanation Table 5 12 Consecutive READ_SAME Accesses With Variable Size Row Command Base Address 00 01...

Page 171: ...can take the target up to one full clock cycle to recognize this edge this synchronization uncertainty is illustrated in Figure 5 6 The target measures delays from this perceived start of the bit time...

Page 172: ...it Timing Logic 1 Figure 5 8 shows the host receiving a logic 0 from the target The host initiates the bit time but the target finishes it Since the target wants the host to receive a logic 0 it drive...

Page 173: ...BDCSI clock cycles followed by a brief speedup pulse on the BKGD pin generated by the target MCU when a command issued by the host has been successfully executed see Figure 5 9 This pulse is referred...

Page 174: ...L is set the BDC gains immediate access if necessary stealing an internal bus cycle NOTE If bus steals are disabled then a loop with no free cycles cannot allow access In this case the host must recog...

Page 175: ...d is assumed to be the 16th BDCSI clock cycle of the last bit The 32 cycle minimum delay differs from the 16 cycle delay time with ACK disabled If a BDC access request does not gain access within 512...

Page 176: ...reset is hardware handshake protocol disabled It can also be disabled by the ACK_DISABLE BDC command This provides backwards compatibility with the existing host devices which are not able to execute...

Page 177: ...ctive BDM The STEP1 command can be issued repeatedly to step through the user code one instruction at a time If an interrupt is pending when a STEP1 command is issued the interrupt stacking operation...

Page 178: ...ase operation is pending completion timeouts are also possible if a BDC command is partially issued or data partially retrieved Thus if a time greater than 512 BDCSI clock cycles is observed between t...

Page 179: ...History Table Revision Number Revision Date Sections Affected Description Of Changes 2 04 19 APR 2012 Section 6 4 5 2 1 Documented DBGTB read dependency on PROFILE bit 2 05 23 MAY 2012 General Format...

Page 180: ...o monitor PC addresses or addresses of data accesses Each comparator can select either read or write access cycles Comparator matches can force state sequencer state transitions Three comparator modes...

Page 181: ...tput of code flow information 6 1 4 Modes of Operation The DBG module can be used in all MCU functional modes The DBG module can issue breakpoint requests to force the device to enter active BDM or an...

Page 182: ...er they occur at the pin Thus an external event occurring less than 2 bus cycles before arming the DBG module is perceived to occur whilst the DBG is armed When the device is in stop mode the synchron...

Page 183: ...C1 C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0 W 0x0109 DBGSCR3 R C3SC1 C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0 W 0x010A DBGEFR R PTBOVF TRIGF 0 EEVF ME3 ME2 ME1 ME0 W 0x010B DBGSR R TBF 0 0 PTACT 0 S...

Page 184: ...COMPE W 0x0121 0x0124 Reserved R 0 0 0 0 0 0 0 0 W 0x0125 DBGBAH R DBGBA 23 16 W 0x0126 DBGBAM R DBGBA 15 8 W 0x0127 DBGBAL R DBGBA 7 0 W 0x0128 0x012F Reserved R 0 0 0 0 0 0 0 0 W 0x0130 DBGCCTL R 0...

Page 185: ...Bit 31 30 29 28 27 26 25 Bit 24 W 0x013D DBGCDM1 R Bit 23 22 21 20 19 18 17 Bit 16 W 0x013E DBGCDM2 R Bit 15 14 13 12 11 10 9 Bit 8 W 0x013F DBGCDM3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0140 DBGDCTL R 0 0 IN...

Page 186: ...Debugger armed 6 TRIG Immediate Trigger Request Bit This bit when written to 1 requests an immediate transition to final state independent of comparator status This bit always reads back a 0 Writing a...

Page 187: ...Table 6 6 1 0 ABCM 1 0 A and B Comparator Match Control These bits determine the A and B comparator match mapping as described in Table 6 7 Table 6 6 CDCM Encoding CDCM Description 00 Match2 mapped to...

Page 188: ...ve no effect in other tracing modes To use a comparator for range filtering the corresponding COMPE bit must remain cleared If the COMPE bit is set then the comparator is used to generate events and t...

Page 189: ...Debug Trace Control Register Low DBGTCRL Table 6 12 DBGTCRL Field Descriptions Field Description 3 DSTAMP Comparator D Timestamp Enable This bit when set enables Comparator D matches to generate time...

Page 190: ...t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W POR X X X X X X X X X X X X X X X X Other Resets Figure 6 7 Debug Trace Buffer Register DBGTB Table 6 13 DBGTB Field Descriptions Field Description 15 0...

Page 191: ...et Thereafter incrementing of CNT continues if configured for end alignment or mid alignment The DBGCNT register is cleared when ARM in DBGC1 is written to a one The DBGCNT register is cleared by powe...

Page 192: ...ect the targeted next state whilst in State1 following a match1 5 4 C2SC 1 0 Channel 2 State Control These bits select the targeted next state whilst in State1 following a match2 7 6 C3SC 1 0 Channel...

Page 193: ...e bits select the targeted next state whilst in State2 following a match3 If EEVE 10 these bits select the targeted next state whilst in State2 following an external event Table 6 19 State2 Match Stat...

Page 194: ...hannel 3 State Control If EEVE 10 these bits select the targeted next state whilst in State3 following a match3 If EEVE 10 these bits select the targeted next state whilst in State3 following an exter...

Page 195: ...generated resets have no affect on this bit 4 PTACT Profiling Transmission Active The PTACT bit when set indicates that the profiling transmission is still active When clear PTACT then profiling tran...

Page 196: ...lue This bit is ignored if the INST bit in the same register is set 0 Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents 5 INS...

Page 197: ...DBGAA 15 8 W Reset 0 0 0 0 0 0 0 0 Address 0x0117 DBGAAL 7 6 5 4 3 2 1 0 R DBGAA 7 0 W Reset 0 0 0 0 0 0 0 0 Figure 6 15 Debug Comparator A Address Register Table 6 27 DBGAAH DBGAAM DBGAAL Field Descr...

Page 198: ...BGAD0 DBGAD1 Comparator Data Bits These bits control whether the comparator compares the data bus bits to a logic one or logic zero The comparator data bits are only used in comparison if the correspo...

Page 199: ...e corresponding data bit Address 0x0120 7 6 5 4 3 2 1 0 R 0 0 INST 0 RW RWE reserved COMPE W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 18 Debug Comparator B Control Register Table 6 30...

Page 200: ...19 18 17 16 R DBGBA 23 16 W Reset 0 0 0 0 0 0 0 0 Address 0x0126 DBGBAM 15 14 13 12 11 10 9 8 R DBGBA 15 8 W Reset 0 0 0 0 0 0 0 0 Address 0x0127 DBGBAL 7 6 5 4 3 2 1 0 R DBGBA 7 0 W Reset 0 0 0 0 0...

Page 201: ...Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents 5 INST Instruction Select This bit configures the comparator to compare PC...

Page 202: ...C Address Register Table 6 35 DBGCAH DBGCAM DBGCAL Field Descriptions Field Description 23 16 DBGCA 23 16 Comparator Address Bits 23 16 These comparator address bits control whether the comparator co...

Page 203: ...ons Field Description 31 16 Bits 31 16 DBGCD0 DBGCD1 Comparator Data Bits These bits control whether the comparator compares the data bus bits to a logic one or logic zero The comparator data bits are...

Page 204: ...to the corresponding comparator data compare bits 0 Do not compare corresponding data bit 1 Compare corresponding data bit Address 0x0140 7 6 5 4 3 2 1 0 R 0 0 INST 0 RW RWE reserved COMPE W Reset 0 0...

Page 205: ...E Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write match 1 0 1 No match 1 1 0 No match 1 1 1 Read match Address 0x0145 DBGDAH 23 22 21 20 19 18...

Page 206: ...that opcode When a match with a comparator register value occurs the associated control logic can force the state sequencer to another state see Figure 6 26 The state sequencer can transition freely...

Page 207: ...is determined by the TRANGE bits in the DBGTCRH register The TRANGE encoding is shown in Table 6 9 If the TRANGE bits select a range definition using comparator D and the COMPE bit is clear then comp...

Page 208: ...eld must be masked using the corresponding data mask registers This ensures that any access of that byte 32 bit 16 bit or 8 bit with matching data causes a match If no bytes are masked then the data c...

Page 209: ...e mask bits can be cleared to ignore bit positions A match occurs when any data bus bit with corresponding mask bit set is different Clearing all mask bits causes all bits to be ignored and prevents a...

Page 210: ...e configured for range comparisons A single match condition on either of the comparators is recognized as valid Outside range mode in combination with opcode address matches can be used to detect if o...

Page 211: ...curs 6 4 3 3 Setting The TRIG Bit Independent of comparator matches it is possible to initiate a tracing session and or breakpoint by writing the TRIG bit in DBGC1 to a logic 1 This forces the state s...

Page 212: ...l State On entering Final State a trigger may be issued to the trace buffer according to the trigger position control as defined by the TALIGN field see Section 6 3 2 3 If tracing is enabled and eithe...

Page 213: ...restricted for example to particular register or RAM range accesses The external event pin can be configured to force trace buffer entries in Normal or Loop1 trace modes All tracing modes support tra...

Page 214: ...before a trigger event 6 4 5 1 3 Storing with End Alignment Storing with End Alignment data is stored in the trace buffer until the Final State is entered Following this trigger the DBG module immedia...

Page 215: ...CE BUFFER ENTRY 3 NOP ADDR1 DBNE D0 PART5 Source address TRACE BUFFER ENTRY 4 IRQ_ISR LD D1 F0 IRQ Vector FFF2 TRACE BUFFER ENTRY 2 ST D1 VAR_C1 RTI The execution flow taking into account the IRQ is a...

Page 216: ...described in Table 6 50 3 CTI Comparator Timestamp Indicator This bit indicates if the trace buffer entry corresponds to a comparator timestamp 0 Trace buffer entry initiated by trace mode specificati...

Page 217: ...d data of data and vector accesses are traced The information byte indicates the size of access and the type of access read or write ADRH ADRM ADRL denote address high middle and low byte respectively...

Page 218: ...rved TSINF1 CPCH1 CPCM1 CPCL1 CDATA32 CDATA22 CDATA12 CDATA02 CINF2 CADRH2 CADRM2 CADRL2 CDATA33 CDATA23 CDATA13 CDATA03 CINF3 CADRH3 CADRM3 CADRL3 Timestamp Timestamp Reserved Reserved TSINF3 CPCH3 C...

Page 219: ...a base address used as a reference for the previous entries on the same line Whilst tracing a base address is typically stored Table 6 54 CINF Field Descriptions Field Description 7 6 CSZ Access Type...

Page 220: ...7 6 5 4 3 2 1 0 CPU CXINF BASE BASE BASE PLB3 PLB2 PLB1 PLB0 7 6 5 4 3 2 1 0 CXINF MAT PLEC NB3 NB2 NB1 NB0 Figure 6 29 Pure PC Mode CXINF Table 6 57 CXINF Field Descriptions Field Description MAT Mi...

Page 221: ...trace buffer is that of the previous instruction The comparator must contain the PC address of the instruction s first opcode byte Timestamps are disabled in Pure PC mode 6 4 5 4 Reading Data from Tra...

Page 222: ...reset during debugging so that it points to the oldest valid data again Debugging occurrences of system resets is best handled using mid or end trigger alignment since the reset may occur before the t...

Page 223: ...d tracing then profiling begins as soon as the module is armed If TALIGN is configured for Begin aligned tracing then profiling begins when the state sequencer enters Final State and continues until a...

Page 224: ...t to Vector Address 8 1 After the PTS entry the pointer increments and the DBG begins to fill the next line with direct COF information This continues until the direct COF field is full or an indirect...

Page 225: ...e stop bit field for each line is shaded In line0 the left most asserted bit is Byte4 7 This indicates that all remaining 31 bits in the 4 byte field contain valid direct COF information whereby each...

Page 226: ...ansition to State0 and associated breakpoints are immediate 6 4 7 2 Breakpoints Generated Via The TRIG Bit When TRIG is written to 1 the Final State is entered If a tracing session is selected by TSOU...

Page 227: ...If an active breakpoint or trigger still exists at that address this can re trigger disarming the DBG If configured for BDM breakpoints the user must apply the BDC STEP1 command to increment the PC p...

Page 228: ...by BDC BACKGROUND commands 6 5 4 Code Profiling The code profiling data output pin PDO is mapped to a device pin that can also be used as GPIO in an application If profiling is required and all pins a...

Page 229: ...ubmitted By Sections Affected Substantial Change s V05 11 21 Aug 2013 changed frequency upper limit of external Pierce Oscillator XOSCLCP from 16MHz to 20MHz fPLLRST changed to fVCORST correct bit num...

Page 230: ...ower consumption and increased emission The Voltage Regulator VREGAUTO has the following features Input voltage range from 6 to 18V nominal operating range Low voltage detect LVD with low voltage inte...

Page 231: ...turn off TC trimming after reset Application can trim the TC if required by overwriting the IRCTRIM register Other features of the S12CPMU_UHV_V5 include Oscillator clock monitor to detect loss of cry...

Page 232: ...red for 50MHz VCOCLK operation Post divider is 0x03 so PLLCLK is VCOCLK divided by 4 that is 12 5MHz and Bus Clock is 6 25MHz The PLL can be re configured for other bus frequencies The reference clock...

Page 233: ...r On Reset POR circuitry is functional The Low Voltage Interrupt LVI and Low Voltage Reset LVR are disabled The API is available The Phase Locked Loop PLL is off The Internal Reference Clock IRC1M is...

Page 234: ...nal RC Oscillator clock During Pseudo Stop Mode the ACLK for the COP can be stopped COP static or running COP active depending on the setting of bit CSAD When bit CSAD is set the ACLK for the COP is s...

Page 235: ...to 18V Autonomous Periodic Interrupt API API Interrupt VSS PLLSEL VSSX VDDA VDDX Low Voltage Detect LVRF PLLCLK Reference Clock IRC1M OSCCLK Monitor osc monitor fail Real Time Interrupt RTI RTI Interr...

Page 236: ...ly Reference Manual Rev 1 05 236 Freescale Semiconductor Figure 7 2 shows a block diagram of the XOSCLCP Figure 7 2 XOSCLCP Block Diagram EXTAL XTAL Gain Control VDD 1 8V Rf OSCCLK Peak Detector VSS V...

Page 237: ...ly 200 k and the XTAL pin is pulled down by an internal resistor of approximately 700 k NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonato...

Page 238: ...put of the voltage regulator that provides the power supply for the internal core logic This supply domain is monitored by the Low Voltage Reset circuit and The Power On Reset circuit 7 2 9 VDDF Inter...

Page 239: ...RVED02 R 0 0 0 0 0 0 0 0 W 0x0003 CPMURFLG R 0 PORF LVRF 0 COPRF 0 OMRF PMRF W 0x0004 CPMU SYNR R VCOFRQ 1 0 SYNDIV 5 0 W 0x0005 CPMU REFDIV R REFFRQ 1 0 0 0 REFDIV 3 0 W 0x0006 CPMU POSTDIV R 0 0 0 P...

Page 240: ...R15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W 0x0015 CPMUAPIRL R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W 0x0016 RESERVED CPMUTEST3 R 0 0 0 0 0 0 0 0 W 0x0017 CPMUHTTR R HTOE 0 0 0 HTT...

Page 241: ...t occurs Unaffected by System Reset Cleared by power on reset 5 PMRF is set to 1 when a PLL clock monitor reset occurs Unaffected by System Reset Cleared by power on reset Unimplemented or Reserved Fi...

Page 242: ...t PLL operation the VCOFRQ 1 0 bits have to be selected according to the actual target VCOCLK 1 OMRF Oscillator Clock Monitor Reset Flag OMRF is set to 1 when a loss of oscillator crystal clock occurs...

Page 243: ...d to configure the internal PLL filter for optimal stability and lock time For correct PLL operation the REFFRQ 1 0 bits have to be selected according to the actual REFCLK frequency as shown in Table...

Page 244: ...HV_V5 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 244 Freescale Semiconductor Table 7 4 Reference Clock Frequency Selection if OSC_LCP is enabled REFCLK Frequency Ranges OSCE 1 REFFRQ 1 0 1MHz fR...

Page 245: ...s up to 32 Bus Clock cycles until fPLL is at the desired target frequency This is because the post divider gradually changes increases or decreases fPLL in order to avoid sudden load changes for the o...

Page 246: ...Writing a 0 has no effect If enabled LOCKIE 1 LOCKIF causes an interrupt request 0 No change in LOCK bit 1 LOCK bit has changed 3 LOCK Lock Status Bit LOCK reflects the current state of PLL lock condi...

Page 247: ...0 0 0 Unimplemented or Reserved Figure 7 9 S12CPMU_UHV_V5 Interrupt Enable Register CPMUINT Table 7 6 CPMUINT Field Descriptions Field Description 7 RTIE Real Time Interrupt Enable Bit 0 Interrupt req...

Page 248: ...be cleared by UPOSC 0 entering Full Stop Mode with COPOSCSEL1 1 or insufficient OSCCLK quality if OSCCLK is used as clock source for other clock domains for instance core clock etc NOTE After writing...

Page 249: ...zation there is a latency time of 2 ACLK cycles to enter Stop Mode After exit from STOP mode when interrupt service routine is entered the software has to wait for 2 ACLK cycles before it is allowed t...

Page 250: ...OSCCLK 0 COP OSCSEL0 COP Clock Select 0 COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP see also Table 7 8 If COPOSCSEL1 1 COPOSCSEL0 has no effect regarding clock select and...

Page 251: ...e should be taken to ensure that the bus frequency does not exceed the specified maximum when frequency modulation is enabled Module Base 0x000A 7 6 5 4 3 2 1 0 R 0 0 FM1 FM0 0 0 0 0 W Reset 0 0 0 0 0...

Page 252: ...or loosing UPOSC status re starts the RTI time out period Module Base 0x000B 7 6 5 4 3 2 1 0 R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W Reset 0 0 0 0 0 0 0 0 Figure 7 12 S12CPMU_UHV_V5 RTI Control R...

Page 253: ...0011 4 OFF 4x210 4x211 4x212 4x213 4x214 4x215 4x216 0100 5 OFF 5x210 5x211 5x212 5x213 5x214 5x215 5x216 0101 6 OFF 6x210 6x211 6x212 6x213 6x214 6x215 6x216 0110 7 OFF 7x210 7x211 7x212 7x213 7x214...

Page 254: ...0x103 100x103 250x103 500x103 1x106 0101 6 6x103 12x103 30x103 60x103 120x103 300x103 600x103 1 2x106 0110 7 7x103 14x103 35x103 70x103 140x103 350x103 700x103 1 4x106 0111 8 8x103 16x103 40x103 80x10...

Page 255: ...Writing CR 2 0 to 000 has no effect but counts for the write once condition Writing WCOP to 0 has no effect but counts for the write once condition When a non zero value is loaded from Flash to CR 2 0...

Page 256: ...OP and CR 2 0 bits while writing the CPMUCOP register It is intended for BDM writing the RSBCK without changing the content of WCOP and CR 2 0 0 Write of WCOP and CR 2 0 has an effect with this write...

Page 257: ...S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 257 Table 7 16 COP Watchdog Rates if COPOSCSEL1 1 CR2 CR1 CR0 COPCLK Cycles to time out COPCLK is ACLK divided by 2 0 0 0 COP disabled...

Page 258: ...e Write Only in Special Mode 7 3 2 12 Reserved Register CPMUTEST1 NOTE This reserved register is designed for factory test purposes only and is not intended for general user access Writing to this reg...

Page 259: ...r to COP end of time out period to avoid a COP reset Sequences of 55 writes are allowed When the WCOP bit is set 55 and AA writes must be done in the last 25 of the selected time out period writing an...

Page 260: ...ernally 1 Bandgap reference voltage VBG can be accessed internally 3 HTE High Temperature Sensor Bandgap Voltage Enable Bit This bit enables the high temperature sensor and bandgap voltage amplifier 0...

Page 261: ...nted or Reserved Figure 7 19 Low Voltage Control Register CPMULVCTL Table 7 18 CPMULVCTL Field Descriptions Field Description 2 LVDS Low Voltage Detect Status Bit This read only status bit reflects th...

Page 262: ...set at the external pin API_EXTCLK periodic high pulses are visible at the end of every selected period with the size of half of the minimum period APIR 0x0000 in Table 7 23 1 If APIEA and APIFE are...

Page 263: ...and Power Management Unit S12CPMU_UHV_V5 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 263 Figure 7 21 Waveform selected on API_EXTCLK pin APIEA 1 APIFE 1 APIES 0 APIES 1 AP...

Page 264: ...ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 0 0 W Reset F F F F F F 0 0 After de assert of System Reset a value is automatically loaded from the Flash memory Figure 7 22 Autonomous Clock Trimming...

Page 265: ...out period of the API will show a latency time between two to three fACLK cycles due to synchronous clock gate release when the API feature gets enabled APIFE bit set Module Base 0x0014 7 6 5 4 3 2 1...

Page 266: ...d 0 0000 0 2 ms1 1 When fACLK is trimmed to 20KHz 0 0001 0 4 ms1 0 0002 0 6 ms1 0 0003 0 8 ms1 0 0004 1 0 ms1 0 0005 1 2 ms1 0 0 FFFD 13106 8 ms1 0 FFFE 13107 0 ms1 0 FFFF 13107 2 ms1 1 0000 2 Bus Clo...

Page 267: ...This reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in Special Mode can alter the S12CPMU_UHV_V5 s functionalit...

Page 268: ...ory See Device specification for details Unimplemented or Reserved Figure 7 26 High Temperature Trimming Register CPMUHTTR Table 7 25 CPMUHTTR Field Descriptions Field Description 7 HTOE High Temperat...

Page 269: ...IRCTRIML Table 7 27 CPMUIRCTRIMH L Field Descriptions Field Description 15 11 TCTRIM 4 0 IRC1M temperature coefficient Trim Bits Trim bits for the Temperature Coefficient TC of the IRC1M frequency Tab...

Page 270: ...anagement Unit S12CPMU_UHV_V5 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 270 Freescale Semiconductor Figure 7 29 IRC1M Frequency Trimming Diagram IRCTRIM 9 0 000 IRCTRIM 9 6 IRCTRIM 5 0 IRC1M fr...

Page 271: ...ive the direction positive or negative of the variation of the TC relative to the nominal TC Setting TCTRIM 4 0 at 0x00000 or 0x10000 does not mean that the temperature coefficient will be zero These...

Page 272: ...4 0 IRC1M Indicative relative TC variation IRC1M indicative frequency drift for relative TC variation 00000 0 nominal TC of the IRC 0 00001 0 27 0 5 00010 0 54 0 9 00011 0 81 1 3 00100 1 08 1 7 00101...

Page 273: ...at ambient temperature which can vary from device to device 7 3 2 22 S12CPMU_UHV_V5 Oscillator Register CPMUOSC This registers configures the external oscillator XOSCLCP Read Anytime Write Anytime if...

Page 274: ...oscillator is disabled REFCLK for PLL is IRCCLK 1 External oscillator is enabled Oscillator clock monitor is enabled External oscillator is qualified by PLLCLK REFCLK for PLL is the external oscillat...

Page 275: ...ytime Module Base 0x001B 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 PROT W Reset 0 0 0 0 0 0 0 0 Figure 7 32 S12CPMU_UHV_V5 Protection Register CPMUPROT Field Description PROT Clock Configuration Registers Prote...

Page 276: ...This reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in Special Mode can alter the S12CPMU_UHV_V5 s functionalit...

Page 277: ...ster CPMUVREGCTL Table 7 30 Effects of writing the EXTXON and INTXON bits value of EXTXON to be written value of INTXON to be written Write Access 0 0 blocked no effect 0 1 legal access 1 0 legal acce...

Page 278: ...or Register 2 CPMUOSC2 Table 7 32 CPMUOSC2 Field Descriptions Field Description 1 OMRE This bit enables the oscillator clock monitor reset If OSCE bit in CPMUOSC register is 1 then the OMRE bit can no...

Page 279: ...of 1 to 16 to generate the reference frequency REFCLK using the REFDIV 3 0 bits Based on the SYNDIV 5 0 bits the PLL generates the VCOCLK by multiplying the reference clock by a 2 4 6 126 128 Based o...

Page 280: ...o the reference clock frequency The circuit determines the lock condition based on this comparison So e g a failure in the reference clock will cause the PLL not to lock If PLL LOCK interrupt requests...

Page 281: ...re 7 36 Startup of clock system after Reset System PLLCLK Reset fVCORST CPU reset state vector fetch program execution LOCK POSTDIV 03 default target fPLL fVCO 4 12 5MHz fPLL increasing fPLL 12 5MHz t...

Page 282: ...e might be an additional significant latency time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization This latency time occurs if COP clock source is ACLK...

Page 283: ...ncy time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization This latency time occurs if COP clock source is ACLK and the CSAD bit is set please refer to C...

Page 284: ...example of how to use the oscillator as source of the Bus Clock is shown in Figure 7 39 Figure 7 39 Enabling the external oscillator PLLSEL OSCE OSCCLK Core enable external oscillator by writing OSCE...

Page 285: ...reference clock for the PLL is based on the external oscillator The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock or the RC...

Page 286: ...PLL lock status LOCK 0 means loosing the oscillator status information as well UPOSC 0 The impact of loosing the oscillator status UPOSC 0 in PBE mode is as follows PLLSEL is set automatically and th...

Page 287: ...he PLLCLK runs with the frequency fVCORST Figure 7 40 RESET Timing 7 5 3 Oscillator Clock Monitor Reset If the external oscillator is enabled OSCE 1 and the oscillator clock monitor reset is enabled O...

Page 288: ...e for the COP is either ACLK IRCCLK or OSCCLK depending on the setting of the COPOSCSEL0 and COPOSCSEL1 bit Depending on the COP configuration there might be a significant latency time until COP is ac...

Page 289: ...COP window setting is allowed except COP off value if the COP was enabled during pre load via NVM memory The COP clock source select bits can not be pre loaded via NVM memory at reset release The IRC...

Page 290: ...IF flag is set to one and a new RTI time out period starts immediately A write to the CPMURTI register restarts the RTI time out period 7 6 1 2 PLL Lock Interrupt The S12CPMU_UHV_V5 generates a PLL Lo...

Page 291: ...o 0 when TJ get below level THTID An interrupt indicated by flag HTIF 1 is triggered by any change of the status bit HTDS if interrupt enable bit HTIE 1 7 6 1 6 Autonomous Periodical Interrupt API The...

Page 292: ...eck that the program is running and sequencing properly Often the COP is kept running during Stop Mode and periodic wake up events are needed to service the COP on time and maybe to check the system s...

Page 293: ...0MHz VCO range 48 to 80 MHz VCOFRQ 1 0 01 CPMUSYNR 0x58 clear all flags especially LOCKIF and OSCIF CPMUIFLG 0xFF put your code to loop and wait for the LOCKIF and OSCIF or poll CPMUIFLG register unti...

Page 294: ...Chapter 7 S12 Clock Reset and Power Management Unit S12CPMU_UHV_V5 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 294 Freescale Semiconductor...

Page 295: ...when the channel is available and when in event mode A full access for the counter registers or the input capture output compare registers should take place in one clock cycle Accessing high byte and...

Page 296: ...it counter 16 bit pulse accumulator on channel 7 8 1 2 Modes of Operation Stop Timer is off because clocks are stopped Freeze Timer counter keeps on running unless TSFRZ in TSCR1 is set to 1 Wait Coun...

Page 297: ...A overflow interrupt Timer overflow interrupt Timer channel 0 interrupt Timer channel 7 interrupt Registers Bus clock Input capture Output compare Input capture Output compare Input capture Output com...

Page 298: ...8 2 16 Bit Pulse Accumulator Block Diagram Figure 8 3 Interrupt Flag Setting Edge detector Intermodule Bus IOC7 M clock Divide by 64 Clock select CLK0 CLK1 4 1 MUX TIMCLK PACLK PACLK 256 PACLK 65536...

Page 299: ...e accumulator input 8 2 2 IOC6 IOC0 Input Capture and Output Compare Channel 6 0 Those pins serve as input capture or output compare for TIM16B8CV3 channel NOTE For the description of interrupts see S...

Page 300: ...OC7D3 OC7D2 OC7D1 OC7D0 W 0x0004 TCNTH R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W 0x0005 TCNTL R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W 0x0006 TSCR1 R TEN TSWAI TSFRZ TFFCA P...

Page 301: ...R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 W 0x002F Reserved R W 1 The register is available only if corresponding channel exists Module Base 0x0000 7 6 5 4 3 2 1 0 R IOS7 IOS6 IOS5 IOS4 IOS3...

Page 302: ...OC 7 0 Note Force Output Compare Action for Channel 7 0 A write to this register with the corresponding data bit s set causes the action which is programmed for output compare x to occur immediately T...

Page 303: ...orresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a channel 7 event Note The corresponding channel must also be setup for output compare IOSx 1 and...

Page 304: ...4 3 2 1 0 R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W Reset 0 0 0 0 0 0 0 0 Figure 8 11 Timer Count Register Low TCNTL Module Base 0x0006 7 6 5 4 3 2 1 0 R TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 W...

Page 305: ...nating software overhead in a separate clear sequence Extra care is required to avoid accidental flag clearing due to unintended accesses 3 PRNT Precision Timer 0 Enables legacy timer PR0 PR1 and PR2...

Page 306: ...output action to be taken as a result of a successful OCx compare When either OMx or OLx is 1 the pin associated with OCx becomes an output tied to OCx Note To enable output action by OMx bits on time...

Page 307: ...x OC7Dx OMx OLx means that both OC7 event and OCx event will change channel x value 8 3 2 9 Timer Control Register 3 Timer Control Register 4 TCTL3 and TCTL4 Read Anytime Table 8 10 The OC7 and OCx ev...

Page 308: ...guration EDGnB EDGnA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge rising or falling Module Base 0x000C 7 6 5 4 3 2 1 0...

Page 309: ...and counter free runs 1 Counter reset by a successful output compare 7 Note If TC7 0x0000 and TCRE 1 TCNT will stay at 0x0000 continuously If TC7 0xFFFF and TCRE 1 TOF will never be set when TCNT is...

Page 310: ...aring mechanism set bits cause corresponding bits to be cleared Module Base 0x000E 7 6 5 4 3 2 1 0 R C7F C6F C5F C4F C3F C2F C1F C0F W Reset 0 0 0 0 0 0 0 0 Figure 8 20 Main Timer Interrupt Flag 1 TFL...

Page 311: ...effect during input capture All timer input capture output compare registers are reset to 0x0000 NOTE Read Write access in byte mode for high byte should take place before low byte otherwise it will...

Page 312: ...se Accumulator Mode This bit is active only when the Pulse Accumulator is enabled PAEN 1 See Table 8 19 0 Event counter mode 1 Gated time accumulation mode 4 PEDGE Pulse Accumulator Edge Control This...

Page 313: ...me When the TFFCA bit in the TSCR register is set any access to the PACNT register will clear all the flags in the PAFLG register Timer module or Pulse Accumulator must stay enabled TEN 1 or PAEN 1 wh...

Page 314: ...the 16 bit pulse accumulator overflows from 0xFFFF to 0x0000 Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to...

Page 315: ...Disconnect Register OCPD Table 8 22 OCPD Field Description Note Writing to unavailable bits has no effect Reading from unavailable bits return a zero Field Description 7 0 OCPD 7 0 Output Compare Pin...

Page 316: ...essary Table 8 23 PTPSR Field Descriptions Field Description 7 0 PTPS 7 0 Precision Timer Prescaler Select Bits These eight bits specify the division rate of the main Timer prescaler These are effecti...

Page 317: ...HANNEL7 TC7 16 BIT COMPARATOR C7F IOC7 PIN LOGIC EDGE DETECT OM OL0 TOV0 OM OL1 TOV1 OM OL7 TOV7 EDG1A EDG1B EDG7A EDG7B EDG0B TCRE PAIF CLEAR COUNTER PAIF PAI INTERRUPT LOGIC CxI INTERRUPT REQUEST PA...

Page 318: ...e or Pulse Accumulator must stay enabled TEN bit of TSCR1 or PAEN bit of PACTL register must be set to one while clearing CxF writing one to CxF 8 4 3 Output Compare Setting the I O select bit IOSx co...

Page 319: ...med before the timer drives OCx The desired state can be programmed to this internal register by writing a one to CFORCx bit with TIOSx OCPDx and TEN bits set to one Set OCx Write a 1 to FOCx while TE...

Page 320: ...NOTE The pulse accumulator counter can operate in event counter mode even when the timer enable bit TEN is clear 8 4 6 Gated Time Accumulation Mode Setting the PAMOD bit configures the pulse accumula...

Page 321: ...ut interrupt The TIM block only generates the interrupt and does not service it 8 6 3 Pulse Accumulator Overflow Interrupt PAOVF This active high output will be asserted by the module to request a tim...

Page 322: ...Chapter 8 Timer Module TIM16B8CV3 Block Description S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 322 Freescale Semiconductor...

Page 323: ...to device specification for exact number Programmable period and duty cycle for each channel Dedicated counter for each PWM channel Programmable PWM enable disable for each channel Software selection...

Page 324: ...channel scalable PWM block Figure 9 1 Scalable PWM Block Diagram 9 2 External Signal Description The scalable PWM module has a selected number of external pins Refer to device specification for exact...

Page 325: ...ster map Reserved bits within a register will always read as 0 and the write will be unimplemented Unimplemented functions are indicated by shading the bit NOTE Register Address Base Address Address O...

Page 326: ...0x000C PWMCNT0 2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x000D PWMCNT12 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x000E PWMCNT22 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x000F PWMCNT32 R B...

Page 327: ...PER52 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001A PWMPER62 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001B PWMPER72 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001C PWMDTY02 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001D PWMDTY12 R Bit 7 6 5 4 3 2...

Page 328: ...sponding 16 bit PWM channel is controlled by the low order PWMEx bit In this case the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled While in run mode...

Page 329: ...Pulse width channel 5 is disabled 1 Pulse width channel 5 is enabled The pulse modulated signal becomes available at PWM output bit 5 when its clock source begins its next cycle 4 PWME4 Pulse Width C...

Page 330: ...ted or stretched pulse can occur during the transition Module Base 0x0001 7 6 5 4 3 2 1 0 R PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W Reset 0 0 0 0 0 0 0 0 Figure 9 4 PWM Polarity Register PWM...

Page 331: ...scale is changed while a PWM signal is being generated a truncated or stretched pulse can occur during the transition Table 9 4 PWMCLK Field Descriptions Note Bits related to available channels have f...

Page 332: ...only when the corresponding channel is disabled Table 9 7 PWMPRCLK Field Descriptions Field Description 6 4 PCKB 2 0 Prescaler Select for Clock B Clock B is one of two clock sources which can be used...

Page 333: ...channel When channels 2 and 3 are concatenated channel 2 registers become the high order bytes of the double byte channel When channels 0 and 1 are concatenated channel 0 registers become the high ord...

Page 334: ...the low order byte Channel 3 output pin is used as the output for this 16 bit PWM bit 3 of port PWMP Channel 3 clock select control bit determines the clock source channel 3 polarity bit determines t...

Page 335: ...the clock source for PWM channel 6 as shown in Table 9 6 5 PCLKAB5 Pulse Width Channel 5 Clock A B Select 0 Clock A or SA is the clock source for PWM channel 5 as shown in Table 9 5 1 Clock B or SB is...

Page 336: ...the scale counter to load the new scale value PWMSCLA Read Anytime Write Anytime causes the scale counter to load the PWMSCLA value 9 3 2 9 PWM Scale B Register PWMSCLB PWMSCLB is the programmable sca...

Page 337: ...formation on the operation of the counters see Section 9 4 2 4 PWM Timer Counters In concatenated mode writes to the 16 bit counter by using a 16 bit access or writes to either the low or high order b...

Page 338: ...Clock Period 2 PWMPERx For boundary case programming values please refer to Section 9 4 2 8 PWM Boundary Cases 1 This register is available only when the corresponding channel exists and is reserved...

Page 339: ...he duty count is reached so the duty registers contain a count of the high time If the polarity bit is zero the output starts low and then goes high when the duty count is reached so the duty register...

Page 340: ...part is in freeze mode by setting the PFRZ bit in the PWMCTL register If this bit is set whenever the MCU is in freeze mode freeze mode signal active the input clock to the prescaler is disabled This...

Page 341: ...X Clock to PWM Ch 0 M U X Clock to PWM Ch 2 M U X Clock to PWM Ch 1 M U X Clock to PWM Ch 4 M U X Clock to PWM Ch 5 M U X Clock to PWM Ch 6 M U X Clock to PWM Ch 7 M U X Clock to PWM Ch 3 Load DIV 2 P...

Page 342: ...ll be E bus clock divided by 4 A pulse will occur at a rate of once every 255x4 E cycles Passing this through the divide by two circuit produces a clock signal at an E divided by 2040 rate Similarly a...

Page 343: ...re 9 16 is the block diagram for the PWM timer Figure 9 16 PWM Timer Channel Block Diagram 9 4 2 1 PWM Enable Each PWM channel has an enable bit PWMEx to start its waveform output When any of the PWME...

Page 344: ...ll always be either the old waveform or the new waveform not some variation in between If the channel is not enabled then writes to the period and duty registers will go directly to the latches as wel...

Page 345: ...riod is started immediately with the output set according to the polarity bit NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur The counter is cleared...

Page 346: ...de for a particular channel take the selected clock source frequency for the channel A B SA or SB and divide it by the value in the period register for that channel PWMx Frequency Clock A B SA or SB P...

Page 347: ...ounter direction from an up count to a down count When the PWM counter decrements and matches the duty register again the output flip flop changes state causing the PWM output to also change state Whe...

Page 348: ...utput waveform generated Figure 9 20 PWM Center Aligned Output Example Waveform 9 4 2 7 PWM 16 Bit Functions The scalable PWM timer also has the option of generating up to 8 channels of 8 bits or 4 ch...

Page 349: ...double byte channel When using the 16 bit concatenated mode the clock source is determined by the low order 8 bit channel clock select control bits That is channel 7 when channels 6 and 7 are concaten...

Page 350: ...bit PWM channel is controlled by the low order PWMEx bit In this case the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled PWMCNT6 PWMCNT7 PWM7 Clock Source 7...

Page 351: ...it concatenation 9 5 Resets The reset state of each individual bit is listed within the Section 9 3 2 Register Descriptions which details the registers and their bit fields All special functions or mo...

Page 352: ...B8CV2 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 352 Freescale Semiconductor For channels 0 1 4 and 5 the clock choices are clock A For channels 2 3 6 and 7 the clock choices are clock B 9 6 Int...

Page 353: ...0 2 Each Interface Signal is associated with one conversion flow control bit For information regarding internal interface connectivity related to the conversion flow control please refer to the device...

Page 354: ...ntrol bits which can be selected according to the application needs Please refer to Section 10 4 2 1 ADC Control Register 0 ADCCTL_0 and Section 10 5 3 2 4 The two conversion flow control Mode Configu...

Page 355: ...curacy Left right justified result data Individual selectable VRH_0 1 and VRL_0 1 inputs on a conversion command basis please see Figure 10 2 Special conversions for selected VRH_0 1 VRL_0 1 VRL_0 1 V...

Page 356: ...d by software before an MCU Stop Mode request As soon as flag SEQAD_IF is set the MCU Stop Mode request can be is issued With the occurrence of the MCU Stop Mode Request until exit from Stop Mode all...

Page 357: ...stored and the corresponding flags are not set Alternatively the Sequence Abort Event can be issued by software before MCU Wait Mode request As soon as flag SEQAD_IF is set the MCU Wait Mode request...

Page 358: ...detect when the Restart Event can be issued without latency time in processing the event see also Figure 10 1 Figure 10 1 Conversion Flow Control Diagram Wait Mode SWAI 1 b1 AUT_RSTA 1 b0 MCU Freeze...

Page 359: ...Trigger Restart Result 63 AN2 AN1 AN0 Conversion RAM DMA access Command Comm_0 Comm_1 Comm 63 Sequence RAM DMA access List Error handler active Active Alternative Sequence Command List Idle LoadOK Flo...

Page 360: ...t Channel x The maximum input channel number is n Please refer to the device reference manual for the maximum number of input channels 10 3 1 2 VRH_0 VRH_1 VRL_0 VRL_1 VRH_0 1 are the high reference v...

Page 361: ...DCCTL_1 R CSL_BMOD RVL_BMOD SMOD_ACC AUT_RSTA 0 0 0 0 W 0x0002 ADCSTS R CSL_SEL RVL_SEL DBECC_ERR Reserved READY 0 0 0 W 0x0003 ADCTIM R 0 PRS 6 0 W 0x0004 ADCFMT R DJM 0 0 0 0 SRES 2 0 W 0x0005 ADCFL...

Page 362: ...d Reserved Reserved W 0x0018 Reserved R Reserved W 0x0019 Reserved R Reserved W 0x001A Reserved R Reserved W 0x001B Reserved R Reserved W 0x001C ADCCIDX R 0 0 CMD_IDX 5 0 W 0x001D ADCCBP_0 R CMD_PTR 2...

Page 363: ...v 1 05 Freescale Semiconductor 363 0x0027 Reserved R Reserved W 0x0028 Reserved R Reserved 0 0 W 0x0029 Reserved R Reserved 0 Reserved W 0x002A 0x003F Reserved R 0 0 0 0 0 0 0 0 W Address Name Bit 7 6...

Page 364: ...th this bit the ADC requires a recovery time period tREC after ADC is enabled until the first conversion can be launched via a trigger 0 ADC disabled 1 ADC enabled 14 ADC_SR ADC Soft Reset This bit ca...

Page 365: ...set by hardware If STR_SEQA 1 b1 and if a Sequence Abort Event or Restart Event is issued during a conversion the data of this conversion is stored and the respective conversion complete flag is set...

Page 366: ...controls register access rights in MCU Special Mode This bit is automatically cleared when leaving MCU Special Mode Note When this bit is set also the ADCCMD register is writeable via the data bus to...

Page 367: ...ult Value List Select Bit This bit controls and indicates which ADC Result List is active This bit can only be written if bit ADC_EN is clear After storage of the initial Result Value List this bit to...

Page 368: ...SMOD_ACC is set Module Base 0x0003 7 6 5 4 3 2 1 0 R 0 PRS 6 0 W Reset 0 0 0 0 0 1 0 1 Unimplemented or Reserved Figure 10 7 ADC Timing Register ADCTIM Table 10 6 ADCTIM Field Descriptions Field Desc...

Page 369: ...Data Justification Conversion result data format is always unsigned This bit controls justification of conversion result data in the conversion result list 0 Left justified data in the conversion res...

Page 370: ...a conversion sequence back to back conversions it takes five Bus Clock cycles plus two ADC conversion clock cycles pump phase from current conversion period end until the newly selected channel is sam...

Page 371: ...trol modes Restart Mode and Trigger Mode when bit RSTA gets set automatically bit SEQA gets set when the ADC has not reached one of the following scenarios A Sequence Abort request is about to be exec...

Page 372: ...uence Command List 1 Restart from top of active Sequence Command List 4 LDOK Load OK for alternative Command Sequence List This bit indicates if the preparation of the alternative Sequence Command Lis...

Page 373: ...odes Can Not Occur 0 0 1 0 Both Modes Valid 5 0 0 1 1 Both Modes Can Not Occur 0 1 0 0 Both Modes Valid 2 0 1 0 1 Both Modes Can Not Occur 0 1 1 0 Both Modes Can Not Occur 0 1 1 1 Both Modes Can Not O...

Page 374: ...nable Bit This bit enables the command value error interrupt 0 Command value interrupt disabled 1 Command value interrupt enabled 5 EOL_EIE End Of List Error Interrupt Enable Bit This bit enables the...

Page 375: ...ble 10 12 ADCIE Field Descriptions Field Description 7 SEQAD_IE Conversion Sequence Abort Done Interrupt Enable Bit This bit enables the conversion sequence abort event done interrupt 0 Conversion seq...

Page 376: ...L_EIF Reserved TRIG_EIF RSTAR_EIF LDOK_EIF 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 12 ADC Error Interrupt Flag Register ADCEIF Table 10 13 ADCEIF Field Descriptions Field Descrip...

Page 377: ...ue of type severe 0 No trigger error occurred 1 A trigger error occurred 2 RSTAR_EIF Restart Request Error Interrupt Flag This flag indicates a flow control issue It is set when a Restart Request occu...

Page 378: ...rsion from top of CSL is stored Module Base 0x0009 7 6 5 4 3 2 1 0 R SEQAD_IF CONIF_OIF Reserved 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 13 ADC Interrupt Flag Register AD...

Page 379: ...nimplemented or Reserved Figure 10 14 ADC Conversion Interrupt Enable Register ADCCONIE Table 10 15 ADCCONIE Field Descriptions Field Description 15 1 CON_IE 15 1 Conversion Interrupt Enable Bits Thes...

Page 380: ...RVL double buffer mode and related registers ADCIMDRI and ADCEOLRI NOTE Overrun situation of a flag CON_IF 15 1 and EOL_IF are indicated by flag CONIF_OIF Module Base 0x000C 15 14 13 12 11 10 9 8 7 6...

Page 381: ...active used RVL buffer at the occurrence of a conversion interrupt flag CON_IF 15 1 occurrence of an intermediate result buffer fill event or when a Sequence Abort Event gets executed 0 RVL_0 active...

Page 382: ...0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 17 ADC End Of List Result Information Register ADCEOLRI Table 10 18 ADCEOLRI Field Descriptions Field Description 7 CSL_EOL Active CSL When End Of...

Page 383: ..._0 Field Descriptions Field Description 31 30 CMD_SEL 1 0 Conversion Command Select Bits These bits define the type of current conversion described in Table 10 20 27 24 INTFLG_SEL 3 0 Conversion Inter...

Page 384: ...uctor Table 10 21 Conversion Interrupt Flag Select CON_IF 15 1 INTFLG_SEL 3 INTFLG_SEL 2 INTFLG_SEL 1 INTFLG_SEL 0 Comment 0x0000 0 0 0 0 No flag set 0x0001 0 0 0 1 Only one flag can be set one hot co...

Page 385: ...d Register 1 ADCCMD_1 Table 10 22 ADCCMD_1 Field Descriptions Field Description 23 VRH_SEL Reference High Voltage Select Bit This bit selects the high voltage reference for current conversion 0 VRH_0...

Page 386: ...g number of analog input channels 0 0 0 1 1 1 Reserved 0 0 1 0 0 0 Internal_0 ADC temperature sense 0 0 1 0 0 1 Internal_1 Vreg_3v3 sense 0 0 1 0 1 0 Internal_2 0 0 1 0 1 1 Internal_3 0 0 1 1 0 0 Inte...

Page 387: ...ion sequence is ongoing Module Base 0x0016 15 14 13 12 11 10 9 8 R SMP 4 0 0 0 Reserved W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 20 ADC Command Register 2 ADCCMD_2 Table 10 24 ADCCM...

Page 388: ...tor 0 1 0 1 0 14 0 1 0 1 1 15 0 1 1 0 0 16 0 1 1 0 1 17 0 1 1 1 0 18 0 1 1 1 1 19 1 0 0 0 0 20 1 0 0 0 1 21 1 0 0 1 0 22 1 0 0 1 1 23 1 0 1 0 0 24 1 0 1 0 1 Reserved 1 0 1 1 0 Reserved 1 0 1 1 1 Reser...

Page 389: ...VHL Family Reference Manual Rev 1 05 Freescale Semiconductor 389 10 4 2 18 ADC Command Register 3 ADCCMD_3 Module Base 0x0017 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved W Reset 0 0 0 0 0 0 0 0 Unimp...

Page 390: ...4 3 2 1 0 R 0 0 CMD_IDX 5 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 22 ADC Command Index Register ADCCIDX Table 10 26 ADCCIDX Field Descriptions Field Description 5 0 CMD_IDX 5 0...

Page 391: ...0 0 0 0 0 Module Base 0x001F 7 6 5 4 3 2 1 0 R CMD_PTR 7 2 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 23 ADC Command Base Pointer Registers ADCCBP_0 ADCCBP_1 ADCCBP_2 Table 10 27...

Page 392: ...5 4 3 2 1 0 R 0 0 RES_IDX 5 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 24 ADC Result Index Register ADCRIDX Table 10 28 ADCRIDX Field Descriptions Field Description 5 0 RES_IDX 5 0...

Page 393: ...15 8 W Reset 0 0 0 0 0 0 0 0 Module Base 0x0023 7 6 5 4 3 2 1 0 R RES_PTR 7 2 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 25 ADC Result Base Pointer Registers ADCRBP_0 ADCRBP_1 AD...

Page 394: ...nversion command and result offset value relative to the conversion command base pointer address and result base pointer address in the memory map to refer to CSL_0 and RVL_0 It is used to calculate t...

Page 395: ...iptions Field Description 6 0 CMDRES_OFF1 6 0 ADC Result Address Offset Value These bits represent the conversion command and result offset value relative to the conversion command base pointer addres...

Page 396: ...ge and charge of the storage node sample capacitor to the voltage level of the analog signal at the selected ADC input channel This architecture employs the advantage of reduced crosstalk between chan...

Page 397: ...ring the sampled and stored analog voltage with a series of binary coded discrete voltages By following a binary search algorithm the A D machine identifies the discrete voltage that is nearest to the...

Page 398: ...SL must contain at least one conversion command and one end of list command type identifier The minimum number of command sequences inside a CSL is zero and the maximum number of command sequences is...

Page 399: ...8 Command_9 Command_10 Command_11 Command_12 Command_13 CSL_0 normal conversion normal conversion Command coding information normal conversion normal conversion normal conversion normal conversion nor...

Page 400: ...er CSL alternative CSL becomes active CSL CSL swapping Which list is actively used for ADC command loading is indicated by bit CSL_SEL The register to define the CSL start addresses ADCCBP can be set...

Page 401: ...ative CSL can be modified to prepare the ADC for new conversion sequences in CSL double buffered mode When the ADC is enabled the command address registers ADCCBP ADCCROFF_0 2 ADCCIDX are read only an...

Page 402: ...ed before entry of Stop or Wait Mode with bit SWAI set is overwritten after exit from the MCU Operating Mode see also Section 10 2 1 2 MCU Operating Modes Which list is actively used for the ADC conve...

Page 403: ...signed data representation Left and right justification inside the entity is selected via the DJM control bit Unused bits inside an entity are stored zero Table 10 32 Conversion Result Justification O...

Page 404: ...e top of current CSL is done automatically Therefore the current CSL can be executed again after the End Of List command type is executed by a Trigger Event only In Restart Mode configuration the exec...

Page 405: ...Bit TRIG is set when no conversion or conversion sequence is ongoing ADC idle and the RVL done condition is reached by one of the following A End Of List command type has been executed A Sequence Abor...

Page 406: ...sion or conversion sequence is ongoing ADC idle and the RVL done condition is reached by one of the following A End Of List command type has been executed A Sequence Abort Event is in progress or has...

Page 407: ...L done condition not reached The RVL done condition is not reached if An End Of List command type has not been executed A Sequence Abort Event has not been executed bit SEQA not already set In all ADC...

Page 408: ...processed and RSTA is set again one cycle later LoadOK Overrun Simultaneously at any Restart Request overrun situation the LoadOK input is evaluated and the status is captured in a background register...

Page 409: ...CSL Load conversion command to background conversion command register 1 The control bit s RSTA and LDOK if set are cleared Wait for Trigger Event to start conversion Generic flow for ADC register loa...

Page 410: ...flags 10 7 1 ADC Conversion Interrupt The ADC provides one conversion interrupt associated to 16 interrupt enable bits with dedicated interrupt flags The 16 interrupt flags consist of 15 conversion in...

Page 411: ...ere issues which cause an error interrupt if enabled and cease ADC operation IA_EIF CMD_EIF EOL_EIF TRIG_EIF In order to make the ADC operational again an ADC Soft Reset must be issued which clears th...

Page 412: ...boundary After an aborted conversion or conversion sequence Figure 10 35 CSL Single Buffer Mode RVL Single Buffer Mode Diagram 10 8 2 List Usage CSL single buffer mode and RVL double buffer mode In th...

Page 413: ...is use case can be used if the channel order or CSL length varies very frequently in an application 10 8 4 List Usage CSL double buffer mode and RVL single buffer mode In this use case the CSL is conf...

Page 414: ...buffer mode the registers ADCIMDRI and ADCEOLRI can be used by the application software to identify which RVL holds relevant and latest data and which CSL is related to this data These registers are u...

Page 415: ..._IF 1 b1 set by hardware cleared by software 1 b1 before next EOL should be cleared by software before Stop Mode entry return to execute from top of CSL followed by next CSL to store first result of o...

Page 416: ...t occur one after the other or simultaneously which causes the ADC to start conversion with commands loaded from CSL_0 If CSL_1 should be executed at the initial conversion start after device reset Bi...

Page 417: ...o start conversion command list execution it is mandatory that the ADC is idle no conversion or conversion sequence is ongoing If necessary a possible ongoing conversion sequence can be aborted by the...

Page 418: ...nding on data transfer rate either use single or double buffer RVL configuration Define a list of conversion commands which only contains the End Of List command with automatic wrap to top of CSL Afte...

Page 419: ...after execution of the End Of List command Figure 10 42 Conversion Flow Control Diagram Triggered Conversion CSL Repetition Figure 10 43 Conversion Flow Control Diagram Triggered Conversion with Stop...

Page 420: ...ore a Restart Event is finished this causes the TRIG_EIF flag being set This allows detection of false flow control sequences Figure 10 44 Conversion Flow Control Diagram Fully Timing Controlled Conve...

Page 421: ...concepts contained within this document Though not exclusively intended for automotive applications CAN protocol is designed to meet the specific requirements of a vehicle serial data bus real time p...

Page 422: ...In First Out Memory IFS Inter Frame Sequence SOF Start of Frame CPU bus CPU related read write data bus CAN bus CAN protocol related serial bus oscillator clock Direct clock from external oscillator...

Page 423: ...ilters Programmable wake up functionality with integrated low pass filter Programmable loopback mode supports self test operation Programmable listen only mode for monitoring of CAN bus Programmable b...

Page 424: ...Pin RXCAN is the MSCAN receiver input pin 11 2 2 TXCAN CAN Transmitter Output Pin TXCAN is the MSCAN transmitter output pin The TXCAN output pin represents the logic level on the CAN bus 0 Dominant s...

Page 425: ...he MSCAN memory map The register address results from the addition of base address and address offset The base address is determined at the MCU level and can be found in the MCU memory map description...

Page 426: ...SEG20 TSEG13 TSEG12 TSEG11 TSEG10 W 0x0004 CANRFLG R WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF W 0x0005 CANRIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0006 CANTFLG R 0 0...

Page 427: ...nternal clocks during a register read 0x000E CANRXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 W 0x000F CANTXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W 0x0010 0x0...

Page 428: ...only It is set when a receiver has received a valid message correctly independently of the filter configuration After it is set it remains set until cleared by software or reset Clearing is done by w...

Page 429: ...ansmission or reception is aborted and synchronization to the CAN bus is lost The module indicates entry to initialization mode by setting INITAK 1 Section 11 3 2 2 MSCAN Control Register 1 CANCTL1 Th...

Page 430: ...ack Self Test Mode When this bit is set the MSCAN performs an internal loopback which can be used for self test operation The bit stream output of the transmitter is fed back to the receiver internall...

Page 431: ...e MSCAN module is in initialization mode see Section 11 4 4 5 MSCAN Initialization Mode It is used as a handshake flag for the INITRQ initialization mode request Initialization mode is active when INI...

Page 432: ...iptions Field Description 7 SAMP Sampling This bit determines the number of CAN bus samples taken per bit time 0 One sample per bit 1 Three samples per bit 1 If SAMP 0 the resulting bit value is equal...

Page 433: ...an associated interrupt enable bit in the CANRIER register 1 In this case PHASE_SEG1 must be at least 2 time quanta Tq Table 11 8 Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq c...

Page 434: ...and requested wake up 6 CSCIF CAN Status Change Interrupt Flag This flag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter TEC and the rec...

Page 435: ...sage is shifted in the receiver FIFO This flag indicates whether the shifted buffer is loaded with a correctly received message matching identifier matching cyclic redundancy code CRC and no other err...

Page 436: ...s off 2 state Discard other receiver state changes for generating CSCIF interrupt 11 Generate CSCIF interrupt on all state changes 2 Bus off state is only defined for transmitters by the CAN standard...

Page 437: ...d is due for transmission The MSCAN sets the flag after the message is sent successfully The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort...

Page 438: ...A transmitter empty transmit buffer available for transmission event causes a transmitter empty interrupt request Module Base 0x0008 Access User read write 1 1 Read Anytime Write Anytime when not in i...

Page 439: ...0 R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 13 MSCAN Transmitter Message Abort Acknowledge Register CANTAAK Table 11 15 CANTAAK Register Field Descriptions Fiel...

Page 440: ...s 0b0000_0110 STAA CANTBSEL value written is 0b0000_0110 LDAA CANTBSEL value read is 0b0000_0010 If all transmit message buffers are deselected no accesses are allowed to the CANTXFG registers 11 3 2...

Page 441: ...rganization see Section 11 4 3 Identifier Acceptance Filter Table 11 18 summarizes the different settings In filter closed mode no message is accepted such that the foreground buffer is never reloaded...

Page 442: ...2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 16 MSCAN Reserved Register Module Base 0x000D Access User read write 1 1 Read Anytime Write Anytime write of 1 clears flag write...

Page 443: ...ay return an incorrect value For MCUs with dual CPUs this may result in a CPU fault condition Module Base 0x000E Access User read write 1 1 Read Only when in sleep mode SLPRQ 1 and SLPAK 1 or initiali...

Page 444: ...y the first two CANIDAR0 1 CANIDMR0 1 are applied Module Base 0x0010 to Module Base 0x0013 Access User read write 1 1 Read Anytime Write Anytime in initialization mode INITRQ 1 and INITAK 1 7 6 5 4 3...

Page 445: ...on is then masked with the corresponding identifier mask register Module Base 0x0014 to Module Base 0x0017 Access User read write 1 1 Read Anytime Write Anytime in initialization mode INITRQ 1 and INI...

Page 446: ...or reception of a message This feature is only available for transmit and receiver buffers if the TIME bit is set see Section 11 3 2 1 MSCAN Control Register 0 CANCTL0 The time stamp register is writ...

Page 447: ...Register Access 0x00X0 IDR0 Identifier Register 0 R W 0x00X1 IDR1 Identifier Register 1 R W 0x00X2 IDR2 Identifier Register 2 R W 0x00X3 IDR3 Identifier Register 3 R W 0x00X4 DSR0 Data Segment Regist...

Page 448: ...IDE 1 ID17 ID16 ID15 W 0x00X2 IDR2 R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 W 0x00X3 IDR3 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W 0x00X4 DSR0 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X5 DSR1 R DB7 DB6 DB5 D...

Page 449: ...it buffer is selected in CANTBSEL see Section 11 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL Unimplemented for receive buffers Reset Undefined because of RAM based implementation 11 3 3 1...

Page 450: ...18 Extended Format Identifier The identifiers consist of 29 bits ID 28 0 for the extended format ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration proced...

Page 451: ...00X3 7 6 5 4 3 2 1 0 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W Reset x x x x x x x x Figure 11 29 Identifier Register 3 IDR3 Extended Identifier Mapping Table 11 29 IDR3 Register Field Descriptions Extended...

Page 452: ...Descriptions Field Description 7 5 ID 2 0 Standard Format Identifier The identifiers consist of 11 bits ID 10 0 for the standard format ID10 is the most significant bit and is transmitted first on the...

Page 453: ...e corresponding DLR register Module Base 0x00X2 7 6 5 4 3 2 1 0 R W Reset x x x x x x x x Unused always read x Figure 11 32 Identifier Register 2 Standard Mapping Module Base 0x00X3 7 6 5 4 3 2 1 0 R...

Page 454: ...tization immediately before the SOF start of frame is sent Module Base 0x00XC 7 6 5 4 3 2 1 0 R DLC3 DLC2 DLC1 DLC0 W Reset x x x x x x x x Unused always read x Figure 11 35 Data Length Register DLR E...

Page 455: ...the time stamp registers Module Base 0x00XD Access User read write 1 1 Read Anytime when TXEx flag is set see Section 11 3 2 7 MSCAN Transmitter Flag Register CANTFLG and the corresponding transmit b...

Page 456: ...nytime when TXEx flag is set see Section 11 3 2 7 MSCAN Transmitter Flag Register CANTFLG and the corresponding transmit buffer is selected in CANTBSEL see Section 11 3 2 11 MSCAN Transmit Buffer Sele...

Page 457: ...Description 11 4 1 General This section provides a complete functional description of the MSCAN 11 4 2 Message Storage Figure 11 39 User Model for Message Buffer Organization MSCAN Rx0 Rx1 CAN Receive...

Page 458: ...second buffer No buffer would then be ready for transmission and the CAN bus would be released At least three transmit buffers are required to meet the first of the above requirements under all circum...

Page 459: ...ages that are already in transmission cannot be aborted the user must request the abort by setting the corresponding abort request bit ABTRQ see Section 11 3 2 9 MSCAN Transmitter Message Abort Reques...

Page 460: ...able to transmit messages while the receiver FIFO is being filled but all incoming messages are discarded As soon as a receive buffer in the FIFO is available again new valid messages will be accepte...

Page 461: ...duces filter 2 and 3 hits Eight identifier acceptance filters each to be applied to the first 8 bits of the identifier This mode implements eight independent filters for the first 8 bits of a CAN 2 0A...

Page 462: ...ier Acceptance Filters ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CANIDAR0 AM7 AM0 CANIDMR0 AC7 AC0 CANIDAR1 AM7 AM0 CANIDM...

Page 463: ...ters CAN 2 0B Extended Identifier CAN 2 0A B Standard Identifier AC7 AC0 CIDAR3 AM7 AM0 CIDMR3 ID Accepted Filter 3 Hit AC7 AC0 CIDAR2 AM7 AM0 CIDMR2 ID Accepted Filter 2 Hit AC7 AC0 CIDAR1 AM7 AM0 CI...

Page 464: ...CANIDMR7 The TXCAN is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode see Section 11 4 5 6 MSCAN Power Down Mode and Section 11 4 4 5 MSCAN...

Page 465: ...SEG This segment has a fixed length of one time quantum Signal edges are expected to happen within this section Time Segment 1 This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard...

Page 466: ...re in compliance with the CAN standard 11 4 4 Modes of Operation 11 4 4 1 Normal System Operating Modes The MSCAN module behaves as described within this specification in all normal system operating m...

Page 467: ...4 4 5 MSCAN Initialization Mode The MSCAN enters initialization mode when it is enabled CANE 1 When entering initialization mode during operation any on going transmission or reception is immediately...

Page 468: ...dication for the request INITRQ to go into initialization mode NOTE The CPU cannot clear INITRQ before initialization mode INITRQ 1 and INITAK 1 is active 11 4 5 Low Power Options If the MSCAN is disa...

Page 469: ...via background debug mode 11 4 5 3 Operation in Stop Mode The STOP instruction puts the MCU in a low power consumption stand by mode In stop mode the MSCAN is set in power down mode regardless of the...

Page 470: ...aring one or more TXEx flag s and immediately request sleep mode by setting SLPRQ Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations If...

Page 471: ...ons If the MSCAN remains in bus off state after sleep mode was exited it continues counting the 128 occurrences of 11 consecutive recessive bits 11 4 5 6 MSCAN Power Down Mode The MSCAN is in power do...

Page 472: ...e of each individual bit is listed in Section 11 3 2 Register Descriptions which details all the registers and their bit fields 11 4 7 Interrupts This section describes all interrupts originated by th...

Page 473: ...1 4 2 3 Receive Structures occurred CAN Status Change The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN As soon as the error counters skip into a criti...

Page 474: ...to the configuration registers in initialization mode 4 Clear INITRQ to leave initialization mode and continue 11 5 2 Bus Off Recovery The bus off recovery is user configurable The bus off state can e...

Page 475: ...should be PT 0 fix typo on page 12 498 should be BKDIF not BLDIF 06 01 05 29 2012 update register map change BD move IREN to SCIACR2 06 02 10 17 2012 fix typo on page 12 480 and on page 12 480 fix ty...

Page 476: ...return to zero NRZ format Selectable IrDA 1 4 return to zero inverted RZI format with programmable pulse widths 16 bit baud rate selection Programmable 8 bit or 9 bit data format Separately enabled tr...

Page 477: ...mode Stop mode 12 1 4 Block Diagram Figure 12 1 is a high level block diagram of the SCI module showing the interaction of various function blocks Figure 12 1 SCI Block Diagram SCI Data Register RXD D...

Page 478: ...n The RXD pin receives SCI standard or infrared data An idle line is detected as a line high This input is ignored when the receiver is disabled and should be terminated to a known voltage 12 3 Memory...

Page 479: ...SBR8 W 0x0001 SCIBDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x0002 SCICR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x0000 SCIASR12 R RXEDGIF 0 0 0 0 BERRV BERRIF BKDIF W 0x0001 SCIACR12 R RXEDG...

Page 480: ...0 Figure 12 4 SCI Baud Rate Register SCIBDL Table 12 2 SCIBDH and SCIBDL Field Descriptions Field Description SBR 15 0 SCI Baud Rate Bits The baud rate for the SCI is determined by the bits in this re...

Page 481: ...ver Source Bit When LOOPS 1 the RSRC bit determines the source for the receiver shift register input See Table 12 4 0 Receiver input internally connected to transmitter output 1 Receiver input connect...

Page 482: ...er the SCI generates and checks for even parity or odd parity With even parity an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit With odd parity an odd number of 1...

Page 483: ...2 BERRV Bit Error Value BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and a mismatch to the expected value happened The value is only meaningful if BERRIF 1...

Page 484: ...ions Field Description 7 RXEDGIE Receive Input Active Edge Interrupt Enable RXEDGIE enables the receive input active edge interrupt flag RXEDGIF to generate interrupt requests 0 RXEDGIF interrupt requ...

Page 485: ...0 Transmitter Narrow Pulse Bits These bits enable whether the SCI transmits a 1 16 3 16 1 32 or 1 4 narrow pulse See Table 12 8 2 1 BERRM 1 0 Bit Error Mode Those two bits determines the functionalit...

Page 486: ...upt requests disabled 1 RDRF and OR interrupt requests enabled 4 ILIE Idle Line Interrupt Enable Bit ILIE enables the idle line flag IDLE to generate interrupt requests 0 IDLE interrupt requests disab...

Page 487: ...empty 6 TC Transmit Complete Flag TC is set low when there is a transmission in progress or when a preamble or break character is loaded TC is set high when the TDRE flag is set and no data preamble o...

Page 488: ...may be at exactly the same time as event 2 or any time after When this happens a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received 2 NF No...

Page 489: ...le of a bit time remaining idle high for a one for inverted polarity 0 Normal polarity 1 Inverted polarity 3 RXPOL Receive Polarity This bit control the polarity of the received data In NRZ format a o...

Page 490: ...T8 is rewritten In 8 bit data format only SCI data register low SCIDRL needs to be accessed Module Base 0x0006 7 6 5 4 3 2 1 0 R R8 T8 0 0 0 Reserved Reserved Reserved W Reset 0 0 0 0 0 0 0 0 Unimple...

Page 491: ...on Interface S12SCIV6 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 491 When transmitting in 9 bit data format and using 8 bit write instructions write first to SCI data reg...

Page 492: ...generator The CPU monitors the status of the SCI writes the data to be transmitted and processes received data Figure 12 14 Detailed SCI Block Diagram SCI Data Receive Shift Register SCI Data Register...

Page 493: ...w pulses during transmission The infrared block receives two clock sources from the SCI R16XCLK and R32XCLK which are configured to generate the narrow pulse width during transmission The R16XCLK and...

Page 494: ...onfigured for 9 bit data characters the ninth data bit is the T8 bit in SCI data register high SCIDRH It remains unchanged after transmission and can be used repeatedly without rewriting it A frame wi...

Page 495: ...n acquisition rate of 16 samples per bit time Baud rate generation is subject to one source of error Integer division of the bus clock may not give the exact target frequency Table 12 16 lists some ex...

Page 496: ...s SCIDRH SCIDRL which in turn are transferred to the transmitter shift register The transmit shift register then shifts a frame out through the TXD pin after it has prefaced them with a start bit and...

Page 497: ...ed to SCIDRH L where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9 bit data format A new transmission will not result until the TDRE flag has been cleared 3 Repeat step 2 for eac...

Page 498: ...er length depends on the M bit in SCI control register 1 SCICR1 As long as SBK is at logic 1 transmitter logic continuously loads break characters into the transmit shift register After software clear...

Page 499: ...all logic 1s and has no start stop or parity bit Idle character length depends on the M bit in SCI control register 1 SCICR1 The preamble is a synchronizing idle character that begins the first transm...

Page 500: ...aborted and the byte in transmit buffer is discarded the transmit data register empty and the transmission complete flag will be set The bit error interrupt flag BERRIF will be set No further transmi...

Page 501: ...XD pin The SCI data register is the read only buffer between the internal data bus and the receive shift register After a complete frame shifts into the receive shift register the data portion of the...

Page 502: ...a valid logic 0 To locate the start bit data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begin...

Page 503: ...bit samples are logic 1s following a successful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit logic 0 To verify a stop bit and to detect noise re...

Page 504: ...sample at RT3 is high The RT3 sample sets the noise flag Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 are within the bit time and data recovery is successful Figure...

Page 505: ...3 Figure 12 25 shows the effect of noise early in the start bit time Although this noise does not affect proper synchronization with the start bit time it does set the noise flag Figure 12 25 Start B...

Page 506: ...he RT8 RT9 and RT10 data samples are ignored Figure 12 27 Start Bit Search Example 6 12 4 6 4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an inc...

Page 507: ...f RT1 but arrives in time for the stop bit data samples at RT8 RT9 and RT10 Figure 12 28 Slow Data Let s take RTr as receiver RT clock and RTt as transmitter RT clock For an 8 bit data character it ta...

Page 508: ...9 the receiver counts 169 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles 176 RTt cycles The maximum percent difference between the receiver count and...

Page 509: ...IDLE or the receive data register full flag RDRF The idle line type bit ILT determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit IL...

Page 510: ...wire operation data from the TXD pin is inverted if RXPOL is set 12 4 8 Loop Operation In loop operation the transmitter output goes to the receiver input The RXD pin is disconnected from the SCI Fig...

Page 511: ...ode for reduced power consumption The STOP instruction does not affect the SCI register states but the SCI bus clock will be disabled The SCI operation resumes from where it left off after an external...

Page 512: ...h level Indicates that an active edge falling for RXPOL 0 rising for RXPOL 1 was detected BERRIF SCIASR1 1 BERRIE Active high level Indicates that a mismatch between transmitted and received data in a...

Page 513: ...interrupt indicates that there is no transmission in progress TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set the TXD pin becomes...

Page 514: ...received data in a single wire application like LIN was detected Clear BERRIF by writing a 1 to the SCIASR1 SCI alternative status register 1 This flag is also cleared if the bit error detect feature...

Page 515: ...t transfer width Bidirectional mode Slave select output Mode fault error flag with CPU interrupt capability Double buffered data register Serial clock with programmable polarity and phase Control of S...

Page 516: ...into run mode If the SPI is configured as a slave reception and transmission of data continues so that the slave stays synchronized to the master Stop mode The SPI is inactive in stop mode for reduced...

Page 517: ...slave 13 2 2 MISO Master In Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master SPI Control Register...

Page 518: ...used by the SPI 13 3 1 Module Memory Map The memory map for the SPI is given in Figure 13 2 The address listed for each register is the sum of a base address and an address offset The base address is...

Page 519: ...ster are reset 0 SPI disabled lower power consumption 1 SPI enabled port pins are dedicated to SPI functions 5 SPTIE SPI Transmit Interrupt Enable This bit enables SPI interrupt requests if SPTEF flag...

Page 520: ...d LSB in the data register Reads and writes of the data register always have the MSB in the highest bit position In master mode a change of this bit will abort a transmission in progress and force the...

Page 521: ...refer to Table 13 3 In master mode a change of this bit will abort a transmission in progress and force the SPI system into idle state 0 SS port pin is not used by the SPI 1 SS port pin with MODF feat...

Page 522: ...escriptions Field Description 6 4 SPPR 2 0 SPI Baud Rate Preselection Bits These bits specify the SPI baud rates as shown in Table 13 7 In master mode a change of these bits will abort a transmission...

Page 523: ...66 kbit s 0 1 1 1 1 0 512 48 83 kbit s 0 1 1 1 1 1 1024 24 41 kbit s 1 0 0 0 0 0 10 2 5 Mbit s 1 0 0 0 0 1 20 1 25 Mbit s 1 0 0 0 1 0 40 625 kbit s 1 0 0 0 1 1 80 312 5 kbit s 1 0 0 1 0 0 160 156 25 k...

Page 524: ...ister For information about clearing SPIF Flag please refer to Table 13 9 0 Transfer not yet complete 1 New data copied to SPIDR 5 SPTEF SPI Transmit Empty Interrupt Flag If set this bit indicates tha...

Page 525: ...tedly without any effect on SPIF SPIF Flag is cleared only by the read of SPIDRL after reading SPISR with SPIF 1 Byte Read SPIDRL or Word Read SPIDRH SPIDRL XFRW Bit SPTEF Interrupt Flag Clearing Sequ...

Page 526: ...If SPIF is set and not serviced and a second data value has been received the second received data is kept as valid data in the receive shift register until the start of another transmission The data...

Page 527: ...en The SPI system is enabled by setting the SPI enable SPE bit in SPI control register 1 While SPE is set the four associated SPI port pins are dedicated to the SPI function as Slave select SS Serial...

Page 528: ...ges see Section 13 4 3 Transmission Formats The SPI can be configured to operate as a master or as a slave When the MSTR bit in SPI control register1 is set master mode is selected when the MSTR bit i...

Page 529: ...e the SPI into idle state The remote slave cannot detect this therefore the master must ensure that the remote slave is returned to idle state 13 4 2 Slave Mode The SPI operates in slave mode when the...

Page 530: ...of the SPI data is driven out of the serial data output pin After the nth1 shift the transfer is considered complete and the received data is transferred into the SPI data register To indicate transfe...

Page 531: ...shift register depending on LSBFE bit After this second edge the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave Th...

Page 532: ...it 5 Bit 2 Bit 6 Bit 1 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 CHANGE O SEL SS I MOSI pin MISO pin Master only MOSI MISO tT If next transfer begins here for tT tl tL Minimum 1 2 SCK tI tL tL M...

Page 533: ...first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay This first edge commands the slave to transfer its first data bit to the serial data input pin of the master A...

Page 534: ...the transfer is complete Figure 13 14 shows two clocking variations for CPHA 1 The diagram may be interpreted as a master or slave timing diagram because the SCK MISO and MOSI pins are connected dire...

Page 535: ...mine the divisor to the SPI module clock which results in the SPI baud rate The SPI clock rate is determined by the product of the value in the baud rate preselection bits SPPR2 SPPR0 and the value in...

Page 536: ...SPI Electrical Specification in the Electricals chapter of this data sheet 13 4 5 Special Features 13 4 5 1 SS Output The SS output feature automatically drives the SS pin low during transmission to s...

Page 537: ...In this case MISO becomes occupied by the SPI and MOSI is not used This must be considered if the MISO pin is used for another purpose 13 4 6 Error Conditions The SPI has one error condition Mode faul...

Page 538: ...4 7 Low Power Mode Options 13 4 7 1 SPI in Run Mode In run mode with the SPI system enable SPE bit in the SPI control register clear the SPI system is in a low power disabled state SPI registers remai...

Page 539: ...the SPI will stay synchronized with the master The stop mode is not dependent on the SPISWAI bit 13 4 7 4 Reset The reset values of registers and signals are described in Section 13 3 Memory Map and...

Page 540: ...ister After SPIF is set it does not clear until it is serviced SPIF has an automatic clearing process which is described in Section 13 3 2 4 SPI Status Register SPISR 13 4 7 5 3 SPTEF SPTEF occurs whe...

Page 541: ...timing The device is capable of operating at higher baud rates up to a maximum of clock 20 with reduced bus loading The maximum communication length and the number of devices that can be connected are...

Page 542: ...d Circuit IICV3 Block Description S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 542 Freescale Semiconductor Acknowledge bit generation detection Bus busy detection General Call Address detection Co...

Page 543: ...tion The IIC functions the same in normal special and emulation modes It has two low power modes wait and stop modes 14 1 3 Block Diagram The block diagram of the IIC module is shown in Figure 14 1 Fi...

Page 544: ...es a detailed description of all memory and registers for the IIC module 14 3 1 Register Descriptions This section consists of register descriptions in address order Each description includes a standa...

Page 545: ...ave Address Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module The default mode of IIC bus is slave mode for an address match on the bus 0 Reserved Reserved Bit 0 of th...

Page 546: ...generated the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to SDA changing the SDA hold time IBC7 6 defines the multiplier factor MUL The values of MUL are s...

Page 547: ...ld value shown in Table 14 7 The equation used to generate the SDA Hold value from the IBFD bits is SDA Hold MUL x scl2tap SDA_Tap 1 x tap2tap 3 The equation for SCL Hold values to generate the start...

Page 548: ...35 10 48 9 18 25 11 56 9 22 29 12 64 13 26 33 13 72 13 30 37 14 80 17 34 41 15 88 17 38 45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1A 112 17 54 57 1B 128 17 62 65 1C 144 25 70 73...

Page 549: ...1022 1025 3C 2304 385 1150 1153 3D 2560 385 1278 1281 3E 3072 513 1534 1537 3F 3840 513 1918 1921 MUL 2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68...

Page 550: ...0 6B 1024 130 508 514 6C 1152 194 572 578 6D 1280 194 636 642 6E 1536 258 764 770 6F 1920 258 956 962 70 1280 130 636 642 71 1536 130 764 770 72 1792 258 892 898 73 2048 258 1020 1026 74 2304 386 1148...

Page 551: ...32 260 98 320 36 152 164 99 384 36 184 196 9A 448 68 216 228 9B 512 68 248 260 9C 576 100 280 292 9D 640 100 312 324 9E 768 132 376 388 9F 960 132 472 484 A0 640 68 312 324 A1 768 68 376 388 A2 896 13...

Page 552: ...F the divider is not changed 14 3 1 3 IIC Control Register IBCR Read and write anytime B2 3584 516 1784 1796 B3 4096 516 2040 2052 B4 4608 772 2296 2308 B5 5120 772 2552 2564 B6 6144 1028 3064 3076 B7...

Page 553: ...is bit is cleared When this bit is changed from 0 to 1 a START signal is generated on the bus and the master mode is selected When this bit is changed from 1 to 0 a STOP signal is generated and the op...

Page 554: ...e transfer Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module 0 Transfer in progress 1 Transfer complete 6 IAAS Addressed as a Slave B...

Page 555: ...SERVED Reserved Bit 3 of IBSR is reserved for future use A read operation on this bit will return 0 2 SRW Slave Read Write When IAAS is set this bit indicates the value of the R W command bit of the c...

Page 556: ...ndard communication is composed of four parts START signal slave address transmission data transfer and STOP signal They are described briefly in the following sections and illustrated in Figure 14 10...

Page 557: ...This signal denotes the beginning of a new data transfer each data transfer may contain several bytes of data and brings all slaves out of their idle states Figure 14 11 Start and Stop Conditions CL...

Page 558: ...rred to as data transfers even if they carry sub address information for the slave device Each data byte is 8 bits long Data may be changed only while SCL is low and must be held stable while SCL is h...

Page 559: ...eceive mode and stop driving SDA output In this case the transition from master to slave mode does not generate a STOP condition Meanwhile a status bit is set by hardware to indicate loss of arbitrati...

Page 560: ...owing rules apply to the first address byte Figure 14 13 Definition of bits in the first byte The address type is identified by ADTYPE When ADTYPE is 0 7 bit address is applied Reversely the address i...

Page 561: ...e first data byte and must be dealt with by S W the IIC hardware does not decode and process the first data byte When one byte transfer is done the received data can be read from IBDR The user can con...

Page 562: ...slave address If 10 bit address is applied IBCR2 should be updated to define the rest bits of address 4 Set the IBEN bit of the IIC bus control register IBCR to enable the IIC interface system 5 Modi...

Page 563: ...t Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit mode i e the address is transmitted If master receive mode is required indicated by R W bit i...

Page 564: ...d of the address cycle where an address match occurred interrupts resulting from subsequent data transfers will have IAAS cleared A data transfer may now be initiated by writing information to IBDR fo...

Page 565: ...inues to be generated until the end of the byte during which arbitration was lost An interrupt occurs at the falling edge of the ninth clock of this transfer with IBAL 1 and MS SL 0 If one master atte...

Page 566: ...ad Data From IBDR And Store Set TXAK 1 Generate Stop Signal 2nd Last Byte To Be Read Last Byte To Be Read Arbitration Lost Clear IBAL IAAS 1 IAAS 1 SRW 1 TX RX Set TX Mode Write Data To IBDR Set RX Mo...

Page 567: ...IICV3 Block Description S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 567 Caution When IIC is configured as 10 bit address the point of the data array in interrupt routine...

Page 568: ...Chapter 14 Inter Integrated Circuit IICV3 Block Description S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 568 Freescale Semiconductor...

Page 569: ...ect frame duty select backplane select and frontplane select enable to produce the required frame frequency and voltage waveforms Table 15 1 LCD40F4BV3 Revision History Version Number Revision Date Ef...

Page 570: ...s 4 backplane drivers Each frontplane has an enable bit respectively Programmable frame clock generator Programmable bias voltage level selector On chip generation of 4 different output voltage levels...

Page 571: ...eference Manual Rev 1 05 Freescale Semiconductor 571 Figure 15 1 LCD40F4BV3 Block Diagram LCD RAM 20 bytes Timing and Control Logic Frontplane Drivers Voltage Generator Backplane Drivers Internal Addr...

Page 572: ...2 3 VLCD LCD Supply Voltage Pin Positive supply voltage for the LCD waveform generation 15 3 Memory Map and Register Definition This section provides a detailed description of all memory and register...

Page 573: ...Read Write 0x0007 Unimplemented 0x0008 LCDRAM Location 0 Read Write 0x0009 LCDRAM Location 1 Read Write 0x000A LCDRAM Location 2 Read Write 0x000B LCDRAM Location 3 Read Write 0x000C LCDRAM Location 4...

Page 574: ...FP22EN FP21EN FP20EN FP19EN FP18EN FP17EN FP16EN W 0x0005 LCDFPENR3 R FP31EN FP30EN FP29EN FP28EN FP27EN FP26EN FP25EN FP24EN W 0x0006 LCDFPENR4 R FP39EN FP38EN FP37EN FP36EN FP35EN FP34EN FP33EN FP32...

Page 575: ...LCDRAM13 R FP27BP3 FP27BP2 FP27BP1 FP27BP0 FP26BP3 FP26BP2 FP26BP1 FP26BP0 W 0x0016 LCDRAM14 R FP29BP3 FP29BP2 FP29BP1 FP29BP0 FP28BP3 FP28BP2 FP28BP1 FP28BP0 W 0x0017 LCDRAM15 R FP31BP3 FP31BP2 FP31...

Page 576: ...neration clocks are stopped 1 LCD driver system is enabled All FP 39 0 pins with FP 39 0 EN set will output an LCD driver waveform The BP 3 0 pins will output an LCD40F4BV3 driver waveform based on th...

Page 577: ...SWAI LCD Stop in Wait Mode This bit controls the LCD operation while in wait mode 0 LCD operates normally in wait mode 1 Stop LCD40F4BV3 driver system when in wait mode 0 LCDRSTP LCD Run in Stop Mode...

Page 578: ...NR0 Module Base 0x0003 7 6 5 4 3 2 1 0 R FP15EN FP14EN FP13EN FP12EN FP11EN FP10EN FP9EN FP8EN W Reset 0 0 0 0 0 0 0 0 Figure 15 6 LCD Frontplane Enable Register 1 LCDFPENR1 Module Base 0x0004 7 6 5 4...

Page 579: ...FP0BP3 FP0BP2 FP0BP1 FP0BP0 LCDRAM W Reset 0 0 0 0 0 0 0 0 0x0009 R FP3BP3 FP3BP2 FP3BP1 FP3BP0 FP2BP3 FP2BP2 FP2BP1 FP2BP0 LCDRAM W Reset 0 0 0 0 0 0 0 0 0x000A R FP5BP3 FP5BP2 FP5BP1 FP5BP0 FP4BP3 F...

Page 580: ...15 R FP27BP3 FP27BP2 FP27BP1 FP27BP0 FP26BP3 FP26BP2 FP26BP1 FP26BP0 LCDRAM W Reset 0 0 0 0 0 0 0 0 0x0016 R FP29BP3 FP29BP2 FP29BP1 FP29BP0 FP28BP3 FP28BP2 FP28BP1 FP28BP0 LCDRAM W Reset 0 0 0 0 0 0...

Page 581: ...is defined by the port integration module PIM 15 4 1 2 LCD Clock and Frame Frequency The frequency of the source clock RTCCLK and divider determine the LCD clock frequency The divider is set by the LC...

Page 582: ...s of the MCU It is possible to read from LCD RAM locations for scrolling purposes When LCDEN 0 the LCD RAM can be used as on chip RAM Writing or reading of the LCDEN bit does not change the contents o...

Page 583: ...e corresponding pins BP 3 0 can be used for other functionality for example as general purpose I O ports 15 4 2 Operation in Wait Mode The LCD40F4BV3 driver system operation during wait mode is contro...

Page 584: ...lock Description S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 584 Freescale Semiconductor 15 4 4 LCD Waveform Examples Figure 15 11 through Figure 15 15 show the timing examples of the LCD output...

Page 585: ...585 15 4 4 1 1 1 Duty Multiplexed with 1 1 Bias Mode Duty 1 1 DUTY1 0 DUTY0 1 Bias 1 1 BIAS 0 or BIAS 1 V0 V1 VSSX V2 V3 VLCD BP1 BP2 and BP3 are not used a maximum of 40 segments are displayed Figure...

Page 586: ...VSSX V1 V2 VLCD 1 2 V3 VLCD BP2 and BP3 are not used a maximum of 80 segments are displayed Figure 15 12 1 2 Duty and 1 2 Bias 0 VLCD VSSX BP0 VLCD VLCD BP0 FPx OFF 1 Frame VLCD 1 2 VLCD VSSX BP1 VLC...

Page 587: ...VHY S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 587 15 4 4 3 1 2 Duty Multiplexed with 1 3 Bias Mode Duty 1 2 DUTY1 1 DUTY0 0 Bias 1 3 BIAS 1 V0 VSSX V1 VLCD 1 3 V2 VLCD 2 3 V3 VL...

Page 588: ...1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 0 VLCD VSSX BP0 VLCD BP0 FPx OFF 1 Frame VLCD 2 3 VLCD 2 3 VLCD 2 3 VLCD VSSX BP1 VLCD 2 3 VLCD VSSX FPx xx10 VLCD 2 3 VLCD VSSX FPy xx00 VLCD 2 3 VLCD VSSX FPz xx11 VLC...

Page 589: ...ias 1 3 BIAS 0 or BIAS 1 V0 VSSX V1 VLCD 1 3 V2 VLCD 2 3 V3 VLCD BP3 is not used a maximum of 120 segments are displayed Figure 15 14 1 3 Duty and 1 3 Bias VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3...

Page 590: ...ual for detailed information In case the clock source is from main OSC after reset the main OSC will be disabled and must be enabled by setting the OSCE in CPMU as soon as possible in order to have cl...

Page 591: ...Freescale Semiconductor 591 15 5 Resets The reset values of registers and signals are described in Section 15 3 Memory Map and Register Definition The behavior of the LCD40F4BV3 system during reset is...

Page 592: ...Chapter 15 Liquid Crystal Display LCD40F4BV3 Block Description S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 592 Freescale Semiconductor...

Page 593: ...cessing only 1 byte output Left right or center aligned PWM This module is suited for but not limited to driving small stepper and air core motors used in instrumentation applications This module can...

Page 594: ...Mode MCOM 11 In this mode two adjacent PWM channels are combined and two PWM channels drive four pins 16 1 2 2 2 Full H Bridge Mode This mode is suitable to drive any load requiring a PWM signal in a...

Page 595: ...595 16 1 3 Block Diagram Figure 16 1 MC10B8C Block Diagram Period Register 11 Bit Timer Counter Duty Register 0 Comparator M0C0M M0C0P Duty Register 1 Comparator M0C1M M0C1P Duty Register 2 Comparator...

Page 596: ...1C0P M1C1M M1C1P PWM Output Pins for Motor 1 High current PWM output pins that can be used for motor drive These pins interface to the coils of motor 1 PWM output on M1C0M results in a positive curren...

Page 597: ...nnel Control Register 1 MCCC1 RW 0x0012 Motor Controller Channel Control Register 2 MCCC2 RW 0x0013 Motor Controller Channel Control Register 3 MCCC3 RW 0x0014 Reserved 0x0015 Reserved 0x0016 Reserved...

Page 598: ...x0031 Reserved 0x0032 Reserved 0x0033 Reserved 0x0034 Reserved 0x0035 Reserved 0x0036 Reserved 0x0037 Reserved 0x0038 Reserved 0x0039 Reserved 0x003A Reserved 0x003B Reserved 0x003C Reserved 0x003D Re...

Page 599: ...entering wait mode both during wait mode and after exiting wait mode 1 Entering wait mode will stop the clock of the module and debias the analog circuitry The module will release the pins 3 FAST Moto...

Page 600: ...1 3 2 Sign Bit S in dual full H bridge modes RECIRC must be changed only while no PWM channel is operating in dual full H bridge mode otherwise erroneous output pattern may occur 0 Recirculation on th...

Page 601: ...CAM 1 0 is set to 0 in all channel control registers after the next period timer counter overflow In this case the motor controller releases all pins NOTE Programming MCPER to 0x0001 and setting the D...

Page 602: ...el Alignment Mode MCAM1 MCAM0 control the PWM channel s PWM alignment mode and operation See Table 16 8 MCAM 1 0 and MCOM 1 0 are double buffered The values used for the generation of the output wavef...

Page 603: ...uty cycle registers define DUTY the number of motor controller timer counter clocks the corresponding output is driven low RECIRC 0 or is driven high RECIRC 1 Setting all bits to 0 will give a static...

Page 604: ...curs while in half H bridge or full H bridge mode A PWM channel pair is configured to work in Dual Full H Bridge mode and a PWM timer counter overflow occurs after the odd1 duty cycle register of the...

Page 605: ...4 1 3 3 RECIRC Bit while in dual full H bridge mode or will be released while in half H bridge mode The state of the S bit in the duty cycle register determines the pin where the PWM signal is driven...

Page 606: ...nal is at a logic high level or motor recirculation currents on the low side drivers RECIRC 1 while the PWM signal is at a logic low level The pin driving the PWM signal is determined by the S sign bi...

Page 607: ...cle working registers are updated whenever a timer counter overflow occurs 16 4 1 1 3 Half H Bridge Mode MCOM 00 or 01 In half H bridge mode the PWM channels x and x 1 operate independently In this mo...

Page 608: ...gnment Modes Each PWM channel can be programmed individually to three different alignment modes The mode is determined by the MCAM 1 0 bits in the corresponding channel control register Left aligned M...

Page 609: ...ct The PWM output signal is generated on MnC0M if the PWM channel number is even n 0 1 2 3 see Table 16 11 or MnC1M if the PWM channel number is odd n 0 1 2 3 Assuming RECIRC 0 the active state of the...

Page 610: ...output on the output terminal not driven by the PWM RECIRC 1 will cause a static low output on the output terminals not driven by the PWM To achieve the same current direction the S bit behavior is in...

Page 611: ...Family Reference Manual Rev 1 05 Freescale Semiconductor 611 Figure 16 12 PWM Active Phase RECIRC 0 S 0 Figure 16 13 PWM Passive Phase RECIRC 0 S 0 VDDM VSSM MnC0P MnC0M Static 0 PWM 1 PWM 1 Static 0...

Page 612: ...Family Reference Manual Rev 1 05 612 Freescale Semiconductor Figure 16 14 PWM Active Phase RECIRC 1 S 0 Figure 16 15 PWM Passive Phase RECIRC 1 S 0 VSSM MnC0P MnC0M VDDM Static 1 Static 1 PWM 0 PWM 0...

Page 613: ...State of Output Transistors in Various Modes Mode MCOM 1 0 PWM Duty RECIRC S T1 T2 T3 T4 Off Don t care Don t care Don t care Half H Bridge 00 Active Don t care Don t care OFF ON Half H Bridge 00 Pass...

Page 614: ...ined in D 10 0 in MCDCx When a match output compare between motor controller timer counter and DUTY occurs the PWM output will toggle to a logic high level and will remain at a logic high level until...

Page 615: ...ter overflows reaches the value defined by P 10 1 1 in MCPER After the motor controller timer counter resets to 0x000 the PWM output will return to a logic low level This process will repeat every num...

Page 616: ...e 16 21 PWM Output DITH 1 MCAM 1 0 11 MCDC 31 MCPER 200 RECIRC 0 PWM Output 1 Period 100 Counts Motor Controller Timer Counter Motor Controller Timer Counter Clock 100 Counts 0 15 16 0 0 16 15 99 99 0...

Page 617: ...WM motor controller timer counter clock source is selected Figure 16 22 Motor Controller Counter Clock Selection The peripheral bus clock is the source for the motor controller counter prescaler The m...

Page 618: ...utput Switching Delay In order to prevent large peak current draw from the motor power supply selectable delays can be used to stagger the high logic level to low logic level transitions on the motor...

Page 619: ...on in Stop and Pseudo Stop Modes All module clocks are stopped and the associated port pins are set to their inactive state which is defined by the state of the RECIRC bit The motor controller module...

Page 620: ...d mode i Dual full H bridge mode MCOM 1 0 11 ii Left aligned PWM MCAM 1 0 01 iii No channel delay MCCD 1 0 00 2 Perform the startup phase a Clear the duty cycle registers MCDC0 and MCDC1 b Initialize...

Page 621: ...be used to monitor the blanking time and the integration time The value in the accumulator represents the change in linked flux magnetic flux times the number of turns in the coil and can be compared...

Page 622: ...Diagram Figure 17 1 SSD Block Diagram Coil SIN Coil COS Bus Clock VDDM COSP COSM T1 T2 T3 VSSM 1 2 1 2 1 2 1 8 4 1 MUX VDDM T4 VSSM S1 S3 S2 S4 VDDM SINP SINM T5 T6 T7 VSSM VDDM T8 VSSM S5 S7 S6 S8 16...

Page 623: ...e coils of a stepper motor to provide four quadrant operation 17 2 1 COSM COSP Cosine Coil Pins for Motor These pins interface to the cosine coils of a stepper motor to measure the back EMF for calibr...

Page 624: ...ess and address offset The base address is determined at the MCU level and is given in the Device Overview chapter The address offset is defined at the block level and is given here 17 3 2 Register De...

Page 625: ...ion 6 DCOIL Drive Coil During return to zero RTZE 1 one of the coils must be driven determined by the STEP field If the DCOIL bit is set this coil is driven If the DCOIL bit is clear this coil is disc...

Page 626: ...OFF ON OFF 10 0 0 1 OFF OFF OFF OFF OFF ON OFF ON 10 0 1 0 OFF ON ON OFF ON OFF ON OFF 10 0 1 1 OFF ON ON OFF OFF ON OFF ON 10 1 1 x OFF ON ON OFF OFF OFF OFF OFF 11 0 0 0 ON OFF ON OFF OFF OFF OFF OF...

Page 627: ...0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 17 3 Modulus Down Counter Control Register MDCCTL Table 17 8 MDCCTL Field Descriptions Field Description 7 MCZIE Modulus Counter Underflow Interrupt E...

Page 628: ...n counter is enabled 1 Modulus down counter is enabled 0 AOVIE Accumulator Overflow Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled An interrupt will be generated when the accumulator overfl...

Page 629: ...ne and cosine coils are recirculated via VSSM 4 FTST Factory Test This bit is reserved for factory test and reads zero in user mode 1 0 ACLKS Accumulator Sample Frequency Select This field sets the ac...

Page 630: ...will stop at 0x0000 If modulus mode is enabled MODMC 1 a write to the MDCCNT register updates the load register with the value written to it The count register will not be updated with the new value...

Page 631: ...epending on the sigma delta conversion sample The accumulator sample frequency is determined by the ACLKS field The accumulator freezes at 0x7FFF on a positive overflow and freezes at 0x8000 on a nega...

Page 632: ...17 4 1 3 Conversion In conversion mode one of the coils is routed for integration with one end connected to the non zero reference input and the other end connected to the integrator input of the sigm...

Page 633: ...s set Figure 17 10 Full Steps CCW Figure 17 11 shows the current flow in the SIN and COS H bridges when STEP 0 DCOIL 1 ITG 0 and RCIR 0 Figure 17 11 Current Flow when STEP 0 DCOIL 1 ITG 0 RCIR 0 Figur...

Page 634: ...TG 0 RCIR 1 Figure 17 13 shows the current flow in the SIN and COS H bridges when STEP 2 DCOIL 1 and ITG 1 Figure 17 13 Current flow when STEP 2 DCOIL 1 ITG 1 Figure 17 14 shows the current flow in th...

Page 635: ...Detector SSDV2 Block Description S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 635 Figure 17 14 Current flow when STEP 3 DCOIL 1 ITG 1 VDDM COSP COSM T1 T2 T3 T4 VSSM VDDM S...

Page 636: ...delta converter and the clock to the modulus counter but due to the converter recovery time the integration result should be ignored Wait mode with SSDWAI bit set powers down the sigma delta converter...

Page 637: ...ibrated zero position 1 Clear or set RCIR clear or set POL 2 Set MCZIE clear MODMC clear or set PRE set MCEN 3 Set RTZE set SDCPU write ACLKS select sample frequency 4 Store threshold value in RAM 1 C...

Page 638: ...Chapter 17 Stepper Stall Detector SSDV2 Block Description S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 638 Freescale Semiconductor...

Page 639: ...error compensation so that the 1 Hz clock could be made more accurate than the frequency accu racy of the crystal that drive the module 18 2 Features Features of the RTC module include 16 bit up coun...

Page 640: ...urrent consumption the RTC should be stopped by software if not needed as an interrupt source during wait mode 18 2 1 2 Stop Modes The RTC continues to run in STOP mode if the RTC is enabled before ex...

Page 641: ...16MHZ main OSC output 18 3 2 OSCCLK_32K The OSCCLK_32K is 32 768K OSC output 16 bit counter 16 bit modulo 16 bit modulo 16 bit comparator 16 bit latch RTCCNT RTCMOD Interrupt Logic SECF SECIE Second C...

Page 642: ...ed information And it is also routed to the pin refer to the device specification for avaiablity and connectivity of signal 18 4 Register Definition The RTC includes status and control registers a 16...

Page 643: ...0 W 0x000D RTCSECR R 0 0 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0 W 0x000E RTCMINR R 0 0 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 W 0x000F RTCHRR R 0 0 0 HR4 HR3 HR2 HR1 HR0 W 7 6 5 4 3 2 1 0 R RTCEN 0 0 0 0 0 COMPE 0 W PO...

Page 644: ...RTCPS0 W POR 0 0 0 0 0 0 0 0 Figure 18 3 RTC Control Register 2 RTCCTL2 Table 18 4 RTCCTL2 Field Descriptions Field Description 7 6 CLKSRC RTC Clock Source Selection The read write bit select the RTC...

Page 645: ...protect sequence 3 FRZ RTC Stop in Freeze Mode The read write bit decide the RTC behavioral during Freeze mode 0 RTC run during freeze mode 1 RTC stop during freeze mode 1 CALS RTC Calibration Clock...

Page 646: ...n compensation circuit start load RTCMOD and RTCCCR to internal buffered register and cleared automatically when finished If this bit is set write to RTCMOD and RTCCCR is blocked Write to this bit has...

Page 647: ...interrupt request Writing a logic 0 has no effect Writing a logic 1 clears the bit and the time base interrupt request Reset clears TB0F to 0 0 No 4 Hz time tick has occurred 1 A 4 Hz time tick has o...

Page 648: ...otect mechanism section 7 6 5 4 3 2 1 0 R RTCCNTL W POR 0 0 0 0 0 0 0 0 Figure 18 8 RTC Counter Register RTCCNT Table 18 9 RTCCNT Field Description Field Description 15 0 RTCCNT RTC Count These sixtee...

Page 649: ...s register can be read at any time without affecting the counter count Writing to this register loads the value to the hour counter and the counter continues to count from this new value Writing value...

Page 650: ...25KHz clock which will be used as RTC counter clock RTCCNT clock input In case the clock source is OSCCLK after reset the main OSC will be disabled and must be enabled by setting the OSCE in CPMU as...

Page 651: ...r first need to decide the CCS which determines the compensation precision The larger CCS value higher the precision longer the compensation period During each compensation cycle the free run timer co...

Page 652: ...the RTC control register 3 RTCCTL3 in a state machine which requires a bit write sequence to disable the write protection A block diagram of the state machine is shown in below Figure Table 18 15 Writ...

Page 653: ...re 18 13 Buffered register load sequence and CDLC 18 6 Initialization Application Information 18 6 1 RTC Calibration 18 6 1 1 ThRev 1 05e off chip calibration The RTC output clock CALCLK can be output...

Page 654: ...h the high precision RTC clock the compensation need following steps Characterization of the OSCCLK or OSCCLK_32K crystal get the lookup table for the crystal frequency versus to temperature This step...

Page 655: ...ly Registers double buffered synchronously reload at edge of tone to avoid distortion of output tone Interrupt generates when SSG is ready to configure new sound data Input clock prescaler with 11 bit...

Page 656: ...or a tone combined with amplitude encoding SGT SGA prescaler counter SSGPS_B SSGAMP_B attack decay logic SSGTONE_B tone counter amplitude logic tone duration counter SSGDUR_B mix bus clock OMS SSGAA_B...

Page 657: ...ss The register detail description follows the order they appear in the register map Reserved bits within a register will always read as 0 and the write will be unimplemented Unimplemented functions a...

Page 658: ...AA7 AA6 AA5 AA4 AA3 AA2 AA1 AA0 W 0x000A SSGATH R 0 0 0 0 0 AT10 AT9 AT8 W 0x000B SSGATL R AT7 AT6 AT5 AT4 AT3 AT2 AT1 AT0 W 0x000C SSGDUR R DUR7 DUR6 DUR5 DUR4 DUR3 DUR2 DUR1 DUR0 W 0x000D SSGIE R 0...

Page 659: ...RESERVED R 0 0 0 0 0 0 0 0 W 0x0016 RESERVED R 0 0 0 0 0 0 0 0 W 0x0017 RESERVED R 0 0 0 0 0 0 0 0 W Module Base 0x0000 7 6 5 4 3 2 1 0 R SSGE 0 0 0 0 OMS RDR STP W Reset 0 0 0 0 0 0 0 0 Figure 19 3...

Page 660: ...d into buffer register 1 Register data is ready to load into buffer register 0 STP SSG STOP 0 SSG runs normally 1 Immediately stop SSG Module Base 0x0001 7 6 5 4 3 2 1 0 R ADE 0 0 0 0 ADM 1 0 ADS W Re...

Page 661: ...Figure 19 5 SSG Clock Prescaler Register SSGPSH Module Base 0x0003 7 6 5 4 3 2 1 0 R PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 W Reset 0 0 0 0 0 0 0 0 Figure 19 6 SSG Clock Prescaler Register SSGPSL Table 19 4...

Page 662: ...SSGTONEH Module Base 0x0005 7 6 5 4 3 2 1 0 R TONE7 TONE6 TONE5 TONE4 TONE3 TONE2 TONE1 TONE0 W Reset 0 0 0 0 0 0 0 0 Figure 19 8 SSG Tone Register SSGTONEL Table 19 6 SSGPS Field Descriptions Field D...

Page 663: ...SGAA The SSGAA is amplitude adjustment register Module Base 0x0006 7 6 5 4 3 2 1 0 R 0 0 0 0 0 AMP10 AMP9 AMP8 W Reset 0 0 0 0 0 0 0 0 Figure 19 9 SSG amplitude Register SSGAMPH Module Base 0x0007 7 6...

Page 664: ...19 12 SSG Amplitude Adjustment SSGAAL Table 19 9 SSGAA Field Descriptions Field Description 10 0 AA 10 0 SSG Amplitude Adjustment Register Bits The bits define the amplitude adjustment value in each...

Page 665: ...nterrupt will be triggered Module Base 0x000C 7 6 5 4 3 2 1 0 R DUR7 DUR6 DUR5 DUR4 DUR3 DUR2 DUR1 DUR0 W Reset 0 0 0 0 0 0 0 0 Figure 19 15 SSG Tone Duration Register SSGDUR Table 19 11 SSGDUR Field...

Page 666: ...set when SSGIF is set Module Base 0x000E 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 RNDI W Reset 0 0 0 0 0 0 0 0 Figure 19 17 SSG Interrupt Flag Register SSGIF Table 19 13 SSGIF Field Descriptions Field Descrip...

Page 667: ...BH Module Base 0x0011 7 6 5 4 3 2 1 0 R AMPB7 AMPB6 AMPB5 AMPB4 AMPB3 AMPB2 AMPB1 AMPB0 W Reset 0 0 0 0 0 0 0 0 Figure 19 19 Buffer Register of SSGAMP SSGAMPBL Table 19 14 SSGAMPB Field Descriptions F...

Page 668: ...the SSGAMP will not disturb the amplitude PWM waveform before the synchronous reload takes place Figure 19 21 SSG Amplitude Generation Table 19 15 SSGDCNT Field Descriptions Field Description 7 0 DCNT...

Page 669: ...the amplitude buffer register can be automatically increased or decreased The amplitude increase implements sound volume attack and the amplitude decrease implements sound volume decay If ADS is clea...

Page 670: ...32 every SSGDUR 1 tone cycle See below gong attack decay formula In exponential attack operation SSGAMPB will multiply with 2 then add 1 every SSGDUR 1 tone cycle In exponential decay operation SSGAMP...

Page 671: ...AMP_int 5 While SSGAMPB AT_buf AT_buf is the internal buffer of amplitude threshold register SSGAT where AMP_int is a 16 bit internal register SSGAMPB SSGAMP Gong decay operation AMP_int SSGAMPB 5 b1...

Page 672: ...eset to 0 when the SSGE is set SSG will restart if RDR is set Clear the SSGE will disable the SGA and SGT output so it is not recommend to use SSGE to stop the SSG The RDR of SSGCR can also stop the S...

Page 673: ...ay mode when amplitude in SSGAMP reaches the SSGAT value and the SSGCR s RDR is set all register will reload to their buffer registers and the interrupt flag RNDI of SSGIF will be set Refer to Figure...

Page 674: ...put selection is determined by OMS of SSGCR When OMS is cleared the SGA output is disable the SGA shared pins can be used as other function 19 5 Interrupt When the RNDI of SSGIF and RNDIE of SSGIE are...

Page 675: ...ry data word The ECC algorithm is able to detect and correct single bit ECC errors Double bit ECC errors will be detected but the system is not able to correct these errors This kind of ECC code is ca...

Page 676: ...ummary Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 ECCSTAT R 0 0 0 0 0 0 0 RDY W 0x0001 ECCIE R 0 0 0 0 0 0 0 SBEEIE W 0x0002 ECCIF R 0 0 0 0 0 0 0 SBEEIF W 0x0003 0x0006 Reserved R 0...

Page 677: ...Figure 20 3 ECC Interrupt Enable Register ECCIE Table 20 3 ECCIE Field Description Module Base 0x00000 Access User read only 1 1 Read Anytime Write Never 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 RDY W Reset 0...

Page 678: ...ld Description Module Base 0x0002 Access User read write 1 1 Read Anytime Write Anytime write 1 to clear 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 SBEEIF W Reset 0 0 0 0 0 0 0 0 Field Description 0 SBEEIF Singl...

Page 679: ...0 0 0 Unimplemented Figure 20 5 ECC Debug Pointer Register ECCDPTRH ECCDPTRM ECCDPTRL Table 20 5 ECCDPTR Register Field Descriptions Field Description DPTR 23 0 ECC Debug Pointer This register contai...

Page 680: ...0 0 0 0 0 0 0 0 Unimplemented Figure 20 6 ECC Debug Data ECCDDH ECCDDL Table 20 6 ECCDD Register Field Descriptions Field Description DDATA 23 0 ECC Debug Raw Data This register contains the raw data...

Page 681: ...function is enabled 1 Automatic single ECC error repair function is disabled 1 ECCDW ECC Debug Write Command Write one to this register bit will perform a debug write access to the system memory Durin...

Page 682: ...he read cycle then the logic generates the new ECC value based on the corrected read and new write read In the next cycle new data word and the new ECC value are written into the memory If required bo...

Page 683: ...e like the read modify write operation of the un aligned access requires that the memory contains valid ECC values before the first read modify write access is performed to avoid spurious ECC error re...

Page 684: ...a and the single bit ECC error is flagged by the SBEEIF but the data inside the system memory are unchanged By writing wrong ECC values into the system memory the debug access can be used to force sin...

Page 685: ...m the memory address defined by register DPTR If the ECCDR bit is cleared then the register DDATA contains the uncorrected read data from the memory The register DECC contains the ECC value read from...

Page 686: ...Chapter 20 ECC Generation module SRAM_ECCV1 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 686 Freescale Semiconductor...

Page 687: ...21 3 2 6 Removed flag DFDIE V02 05 11 Jul 2012 Added explanation about when MGSTAT 1 0 bits are cleared Section 21 3 2 7 Added note about possibility of reading P Flash and EEPROM simultaneously Secti...

Page 688: ...us cycle for bytes and aligned words For misaligned words access the CPU has to perform twice the byte read access command For Flash memory an erased bit reads 1 and a programmed bit reads 0 It is pos...

Page 689: ...rection and double bit fault detection within a 32 bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phra...

Page 690: ...Diagram 21 2 External Signal Description The Flash module contains no signals that connect off chip Bus Clock Divider Clock Command Interrupt Request FCLK Protection Security Registers Flash Interface...

Page 691: ...he reset sequence 21 3 1 Module Memory Map The S12Z architecture places the P Flash memory between global addresses 0xFF_0000 and 0xFF_FFFF as shown in Table 21 3 The P Flash memory map is shown in Fi...

Page 692: ...7 8 Backdoor Comparison Key Refer to Section 21 4 7 11 Verify Backdoor Access Key Command and Section 21 5 1 Unsecuring the MCU using Backdoor Key Access 0xFF_FE08 0xFF_FE091 2 Protection Override Com...

Page 693: ...d Unprotected Lower Region 1 2 4 8 KB 0xFF_8000 0xFF_9000 0xFF_8400 0xFF_8800 0xFF_A000 P Flash END 0xFF_FFFF 0xFF_F800 0xFF_F000 0xFF_E000 Flash Protected Unprotected Higher Region 2 4 8 16 KB Flash...

Page 694: ...n 21 4 2 0x1F_C0B8 0x1F_C0BF 8 Reserved 0x1F_C0C0 0x1F_C0FF 64 Program Once Field Refer to Section 21 4 7 6 Program Once Command Table 21 6 Memory Controller Resource Fields NVM Resource Area 1 1 See...

Page 695: ...Flash command execution for more detail see Caution note in Section 21 3 A summary of the Flash module registers is given in Figure 21 4 with detailed descriptions in the following subsections Addres...

Page 696: ...FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0009 DFPROT R DPOPEN 0 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0 W 0x000A FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W 0x000B FRSV1 R 0 0 0 0 0 0 0 0 W 0x000C FCCOB0HI R CCOB15 CCO...

Page 697: ...CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0012 FCCOB3HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0013 FCCOB3LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0014 FCCOB4HI R CCOB15...

Page 698: ...vely divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms Table 21 8 shows recommended values for FDIV 5 0 based on the BUSCLK frequency Please refer to Sectio...

Page 699: ...ve the Flash module in a secured state with backdoor key access disabled 18 6 19 6 0x12 44 6 45 6 0x2C 19 6 20 6 0x13 45 6 46 6 0x2D 20 6 21 6 0x14 46 6 47 6 0x2E 21 6 22 6 0x15 47 6 48 6 0x2F 22 6 23...

Page 700: ...nts 1 0 SEC 1 0 Flash Security Bits The SEC 1 0 bits define the security state of the MCU as shown in Table 21 11 If the Flash module is unsecured using backdoor key access the SEC bits are forced to...

Page 701: ...eld Description 7 FPOVRD Flash Protection Override Status The FPOVRD bit indicates if the Protection Override feature is currently enabled See Section 21 4 7 17 Protection Override Command for more de...

Page 702: ...Field to the unsecure state d release MCU security by setting the SEC field of the FSEC register to the unsecure state as defined in Table 21 9 of Section 21 3 2 2 The ERSAREQ bit sets to 1 when soc_e...

Page 703: ...sociated interrupt routine The FSFD bit is cleared by writing a 0 to FSFD 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash a...

Page 704: ...Flag The CCIF flag indicates that a Flash command has completed The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violatio...

Page 705: ...that was under a Flash command operation 1 The DFDF flag is cleared by writing a 1 to DFDF Writing a 0 to DFDF has no effect on DFDF 2 0 No double bit fault detected 1 Double bit fault detected or a...

Page 706: ...e set in the FSTAT register The block erase of a P Flash block is not possible if any of the P Flash sectors contained in the same P Flash block are protected Offset Module Base 0x0008 7 6 5 4 3 2 1 0...

Page 707: ...ss Size The FPLS bits determine the size of the protected unprotected area in P Flash memory as shown in Table 21 22 The FPLS bits can only be written to while the FPLDIS bit is set Table 21 20 P Flas...

Page 708: ...6 5 4 FPHS 1 0 FPLS 1 0 3 2 1 0 FPHS 1 0 FPLS 1 0 FPHDIS 1 FPLDIS 1 FPHDIS 1 FPLDIS 0 FPHDIS 0 FPLDIS 1 FPHDIS 0 FPLDIS 0 Scenario Scenario Unprotected region Protected region with size Protected regi...

Page 709: ...n be added but not removed Writes must increase the DPS value and the DPOPEN bit can only be written from 1 protection disabled to 0 protection enabled If the DPOPEN bit is set the state of the DPS bi...

Page 710: ...ctors are protected 21 3 2 11 Flash Option Register FOPT The FOPT register is the Flash option register Table 21 24 DFPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Ena...

Page 711: ...ster FRSV1 This Flash register is reserved for factory testing All bits in the FRSV1 register read 0 and are not writable 21 3 2 13 Flash Common Command Object Registers FCCOB The FCCOB is an array of...

Page 712: ...W Reset 0 0 0 0 0 0 0 0 Figure 21 19 Flash Common Command Object 0 Low Register FCCOB0LO Offset Module Base 0x000E 7 6 5 4 3 2 1 0 R CCOB 15 8 W Reset 0 0 0 0 0 0 0 0 Figure 21 20 Flash Common Comman...

Page 713: ...W Reset 0 0 0 0 0 0 0 0 Figure 21 24 Flash Common Command Object 3 High Register FCCOB3HI Offset Module Base 0x0013 7 6 5 4 3 2 1 0 R CCOB 7 0 W Reset 0 0 0 0 0 0 0 0 Figure 21 25 Flash Common Comman...

Page 714: ...e available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller The value written to the FCCOBIX field must reflect the amount of CCOB words loaded fo...

Page 715: ...1 with both 0b_0000 and 0b_1111 meaning none 21 4 3 Flash Block Read Access If data read from the Flash block results in a double bit fault ECC error meaning that data is detected to be in error and c...

Page 716: ...ads the value of FPSTAT WSTATACK the new wait state configuration will be effective when it reads as 1 user must re write FCLKDIV to set a new value based on the lower frequency The following sequence...

Page 717: ...FCLKDIV register has not been written any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set 21 4 5 2 Command Wri...

Page 718: ...or and Protection Violation Read FSTAT register START Check FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no FDIV Correct no Bit Polling for Command Completion Check ye...

Page 719: ...ed Secured NS 1 1 Unsecured Normal Single Chip mode SS 2 2 Unsecured Special Single Chip mode NS 3 3 Secured Normal Single Chip mode SS 4 4 Secured Special Single Chip mode Please refer to Section 21...

Page 720: ...byte field in the nonvolatile information register in P Flash block that is allowed to be programmed only once 0x08 Erase All Blocks Erase all P Flash and EEPROM blocks An erase of all Flash blocks i...

Page 721: ...reading Table 21 31 EEPROM Commands FCMD Command Function on EEPROM Memory 0x01 Erase Verify All Blocks Verify that all EEPROM and P Flash blocks are erased 0x02 Erase Verify Block Verify that the EE...

Page 722: ...AT register the user must clear these bits before starting any command write sequence see Section 21 3 2 7 CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative...

Page 723: ...l be set Table 21 33 Erase Verify All Blocks Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x01 Not required Table 21 34 Erase Verify All Blocks Command Error Handling Register Error Bit...

Page 724: ...4 7 6 The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway Table 21 37 Erase Verify P Flash Section Command FCCOB Requiremen...

Page 725: ...amming of bits within a Flash phrase is not allowed FCCOB3 Read Once word 1 value FCCOB4 Read Once word 2 value FCCOB5 Read Once word 3 value Table 21 40 Read Once Command Error Handling Register Erro...

Page 726: ...th read back The CCIF flag will remain clear setting only after the Program Once operation has completed The reserved nonvolatile information register accessed by the Program Once command cannot be er...

Page 727: ...nce Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 101 at command launch Set if command not available in current mode see Table 21 29 Set if an invalid phrase...

Page 728: ...ed in the ERSAREQ bit in the FCNFG register see Section 21 3 2 5 The ERSAREQ bit in FCNFG will be cleared once the operation has completed and the normal FSTAT error reporting will be available as des...

Page 729: ...a of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non correctable errors have been encountered during the verify...

Page 730: ...cess Key command will only execute if it is enabled by the KEYEN bits in the FSEC register see Table 21 10 The Verify Backdoor Access Key command releases security if user supplied keys match those st...

Page 731: ...ture read operations of the P Flash or EEPROM block Upon clearing CCIF to launch the Set User Margin Level command the Memory Controller will set the user margin level for the targeted block and then...

Page 732: ...ler will set the field margin level for the targeted block and then set the CCIF flag Table 21 57 Valid Set User Margin Level Settings FCCOB2 Level Description 0x0000 Return to Normal Level 0x0001 Use...

Page 733: ...nts have adequate margin for data retention at the normal level setting If unexpected results are encountered when checking Flash memory contents at field margin levels the Flash memory contents shoul...

Page 734: ...onfirm that the targeted location s were successfully programmed upon completion CAUTION A Flash word must be in the erased state before being programmed Cumulative programming of bits within a Flash...

Page 735: ...3 Word 1 program value if desired FCCOB4 Word 2 program value if desired FCCOB5 Word 3 program value if desired Table 21 65 Program EEPROM Command Error Handling Register Error Bit Error Condition FST...

Page 736: ...n Override feature to be disabled Current status of the Protection Override feature can be observed on FPSTAT FPOVRD bit see Section 21 3 2 4 Flash Protection Status Register FPSTAT Table 21 67 Erase...

Page 737: ...can be called multiple times and every time it is launched it will preserve the current values of registers FPROT and DFPROT in a single entry buffer to be restored later when the Protection Override...

Page 738: ...description of the register bits involved refer to Section 21 3 2 5 Flash Configuration Register FCNFG Section 21 3 2 6 Flash Error Configuration Register FERCNFG Section 21 3 2 7 Flash Status Regist...

Page 739: ...of the backdoor keys four 16 bit words programmed at addresses 0xFF_FE00 0xFF_FE07 If the KEYEN 1 0 bits are in the enabled state see Section 21 3 2 2 the Verify Backdoor Access Key command see Secti...

Page 740: ...ed in Section 21 4 7 7 1 Erase All Pin For a complete description about how to activate that procedure please look into the Reference Manual 21 5 3 Mode and Security Effects on Flash Command Availabil...

Page 741: ...1 Run mode The activation of the VSENSE Level Sense Enable BSESE 1 or ADC connection Enable BSEAE 1 closes the path from the VSENSE pin through the resistor chain to ground and enables the associated...

Page 742: ...o ADC channel Figure 22 1 BATS Block Diagram 22 2 External Signal Description This section lists the name and description of all external ports 22 2 1 VSENSE Supply Battery Voltage Sense Pin This pin...

Page 743: ...tection 22 2 2 VSUP Voltage Supply Pin This pin is the chip supply It can be internally connected for voltage measurement The voltage present at this input is scaled down by an internal voltage divide...

Page 744: ...ludes a standard register diagram with an associated figure number Details of register bit and field function follow the register diagrams in bit order Unused bits read back zero Address Offset Regist...

Page 745: ...Connection Enable This bit connects the VSUP pin through the resistor chain to ground and connects the ADC channel to the divided down voltage This bit can be set only if the BSEAE bit is cleared 0 AD...

Page 746: ...le Semiconductor When opening the resistors path to ground by changing BSESE BSEAE or BSUSE BSUAE then for a time TEN_UNC two bus cycles the measured value is invalid This is to let internal nodes be...

Page 747: ...r Field Descriptions Field Description 1 BVHC BATS Voltage Sense High Condition Bit This status bit indicates that a high voltage at VSENSE or VSUP depending on selection is present 0 Vmeasured VHBI_A...

Page 748: ...Register Field Descriptions Field Description 1 BVHIE BATS Interrupt Enable High Enables High Voltage Interrupt 0 No interrupt will be requested whenever BVHIF flag is set 1 Interrupt will be requeste...

Page 749: ...TS module can be configured to generate a low and high voltage interrupt based on VSENSE or VSUP The trigger level of the high and low interrupt are selectable In a typical application the module coul...

Page 750: ...fined at MCU level The module internal interrupt sources are combined into one module interrupt signal 22 4 2 1 BATS Voltage Low Condition Interrupt BVLI To use the Voltage Low Interrupt the Level Sen...

Page 751: ...or BSUSE If measured when a VHBI1 selected with BVHS 0 at selected pin Vmeasure VHBI1_A rising edge or Vmeasure VHBI1_D falling edge or when a VHBI2 selected with BVHS 1 at selected pin Vmeasure VHBI2...

Page 752: ...Chapter 22 Supply Voltage Sensor BATSV2 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 752 Freescale Semiconductor...

Page 753: ...00 25 June 2012 All Added LIN TxD dominant timeout feature V02 06 11 Jan 2013 All Added application note to help the ISR development for the Interrupts timeout and overcurrent V02 08 10 Apr 2013 Regi...

Page 754: ...fall time from recessive to dominant and the rise time from dominant to recessive is selectable and controlled to guarantee communication quality and reduce EMC emissions The symmetry between both sl...

Page 755: ...k diagram of the LIN Physical Layer The module consists of a receiver with wake up control a transmitter with slope and timeout control a current sensor with overcurrent protection as well as a regist...

Page 756: ...und and filter noise 23 2 3 VLINSUP Positive Power Supply External power supply to the chip The VLINSUP supply mapping is described in device level documentation 23 2 4 LPTxD LIN Transmit Pin This pin...

Page 757: ...er Address Module Base Address Address Offset where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level Address Offset Register Name Bit 7 6 5 4 3...

Page 758: ...1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 LPDR1 LPDR0 W Reset 0 0 0 0 0 0 1 1 Unimplemented Figure 23 3 Port LP Data Register LPDR Field Description 1 LPDR1 Port LP Data Bit 1 The...

Page 759: ...Physical Layer functions are available except that the bus line is held in its recessive state by a high ohmic 330k resistor All registers are normally accessible 1 The LIN Physical Layer is not in sh...

Page 760: ...ad write 1 1 Read Anytime Write Only in special mode 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W Reset x x x x x x x x Unimplemented Figure 23 5 LIN Tes...

Page 761: ...see section 23 4 2 for details on how the slew rate control works These bits are only writable in shutdown mode LPE 0 00 Normal Slew Rate optimized for 20 kbit s 01 Slow Slew Rate optimized for 10 4 k...

Page 762: ...nimplemented Figure 23 8 LIN Status Register LPSR Table 23 7 LPSR Field Description Field Description 7 LPDT LIN Transmitter TxD dominant timeout Status Bit This read only bit signals that the LPTxD p...

Page 763: ...4 3 2 1 0 R LPDTIE LPOCIE 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 23 9 LIN Interrupt Enable Register LPIE Table 23 8 LPIE Field Description Field Description 7 LPDTIE LIN transmitter...

Page 764: ...LPDTIF is not allowed if LPDTIF 0 already If the LPTxD is still dominant after clearing the flag the transmitter stays disabled and this flag is set again see 23 4 4 2 TxD dominant timeout Interrupt...

Page 765: ...pdated the LIN Physical Layer can be enabled again NOTE For 20 kbit s and Fast Mode communication speeds the corresponding slew rate MUST be set otherwise the communication is not guaranteed violation...

Page 766: ...shutdown mode 23 4 3 2 Normal Mode The full functionality is available Both receiver and transmitter are enabled The internal pullup resistor can be chosen to be high ohmic 330 k if LPPUE 0 or LIN co...

Page 767: ...e up enabled If LPWUE 0 the internal pullup resistor is not selectable and remains at 330 k regardless of the state of the LPPUE bit If LPWUE 1 selecting the 330 k pullup resistor LPPUE 0 reduces the...

Page 768: ...Chapter 23 LIN Physical Layer S12LINPHYV2 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 768 Freescale Semiconductor Figure 23 11 LIN Physical Layer Mode Transitions...

Page 769: ...re enable the transmitter again the following prerequisites must be met 1 Overcurrent condition is over 2 LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum...

Page 770: ...r more than tDTLIM the transmitter is disabled and the LPDT status flag and the LPDTIF interrupt flag are set In order to re enable the transmitter again the following prerequisites must be met 1 TxD...

Page 771: ...de the transmitter remains disabled and the LPDTIF flag is set after a time again to indicate that the attempt to re enable has failed This time is equal to minimum 1 IRC period 1 us 2 bus periods max...

Page 772: ...ying to clear an error flag always make sure that it is already set 23 5 2 Interrupt handling in Interrupt Service Routine ISR Both interrupts TxD dominant timeout and overcurrent represent a failure...

Page 773: ...lag 5 Enable the interrupts again LPDTIE and LPOCIE 6 Enable the LIN Physical Layer or leave the receive only mode LPCR register 7 Wait for a minimum of a transmit bit before beginning transmission ag...

Page 774: ...Chapter 23 LIN Physical Layer S12LINPHYV2 S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 774 Freescale Semiconductor...

Page 775: ...a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification is shown in the column labeled C in the p...

Page 776: ...n for 2 8V core supply voltage generated by on chip voltage regulator VSS2 0V Ground pin for 1 8V core supply voltage generated by on chip voltage regulator LGND 0V Ground pin for LINPHY VDDX1 1 1 VDD...

Page 777: ...PIO pin Assume Px is configured as an input The pad driver transistors P1 and N1 are switched off high impedance If the voltage Vin on Px is greater than VDDX a positive injection current Iin will flo...

Page 778: ...cation Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature unless specified otherwise in the device speci...

Page 779: ...nce C 4 pF Latch up for 5V GPIO s Minimum Input Voltage Limit 2 5 V Maximum Input Voltage Limit 7 5 V Latch up for BCTL VSENSE LIN Minimum Input Voltage Limit 7 V Maximum Input Voltage Limit 21 V Tabl...

Page 780: ...single pulse tmax 400ms V 2 main Oscillator fosc 4 20 MHz 3 32K Oscillator fosc32k 32 40 KHz 4 Bus frequency fbus see Footnote 2 2 Minimum bus frequency for ADC module refer to fADCCLK and for Flash p...

Page 781: ...nent Description PSUP VSUP ISUP Internal Power through VSUP pin PBCTL VBCTL IBCTL Internal Power through BCTL pin PINT VDDX IVDDX VDDA IVDDA VDDM IVDDM Internal Power through VDDX A M pins PGPIO VI O...

Page 782: ...pecification JESD51 7 in a horizontal configuration in natural convection JA 45 C W 3 D Junction to Board 100LQFP JB 30 C W 4 D Junction to Case 100LQFP4 JC 13 C W 144LQFP 5 D Thermal resistance 144LQ...

Page 783: ...l except PU Vin VDD35 or VSS35 V Temperature range 40 C to 105 C I in 1 1 A P Input leakage current pins in high impedance input mode 2 PU Vin VDD35 or VSS35 V Temperature range 40 C to 105 C I in 2 5...

Page 784: ...re 2 Maximum leakage current occurs at maximum operating temperature 3 Refer to Section A 1 3 Current Injection for more details For sake of ADC conversion accuracy the application should avoid to inj...

Page 785: ...uency is 64MHz Table A 10 Table A 11 and Table A 12 show the configuration of the CPMU module and the peripherals for Run Wait and Stop current measurement Table A 10 CPMU Configuration for Pseudo Sto...

Page 786: ...d and the comparators are configured to trigger in outside range The range covers all the code executed by the core TIM The peripheral is configured to output compare mode pulse accumulator and modulu...

Page 787: ...ISUPS 35 A Table A 15 Pseudo Stop Current Characteristics Conditions are VSUP 12V API COP RTI enabled Num C Rating Symbol Min Typ Max Unit Pseudo Stop Current with API COP and RTI enabled 1 C TA 25 C...

Page 788: ...Appendix A MCU Electrical Specifications S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 788 Freescale Semiconductor...

Page 789: ...ADC A further factor is that PortAD pins that are configured as output drivers switching Supply voltage 4 5V VDDA 5 5 V 40o C TJ 150o C Num C Rating Symbol Min Typ Max Unit 1 D Reference potential Low...

Page 790: ...nal and the pin capacitance For a maximum sampling error of the input voltage 1LSB 10 bit resilution then the external filter capacitor Cf 1024 CINS CINN B 1 1 4 Current Injection There are two cases...

Page 791: ...ing any errors due to current injection input capacitance and source resistance B 1 2 1 ADC Accuracy Definitions For the following definitions see also Figure B 1 Differential non linearity DNL is def...

Page 792: ...Vin mV 10 15 20 25 30 35 40 85 90 95 100 105 110 115 120 65 70 75 80 60 0 3 2 5 4 7 6 45 3F7 3F9 3F8 3FB 3FA 3FD 3FC 3FE 3FF 3F4 3F6 3F5 8 9 1 2 FF FE FD 3F3 10 Bit Resolution 8 Bit Resolution Ideal...

Page 793: ...turally tested in production test Absolute values are tested in 10 bit mode Symbol Min Typ Max Unit 5 P Resolution VREF 5 12V 10 Bit LSB 5 mV 6 P Differential Nonlinearity 10 Bit DNL 1 0 5 1 counts 7...

Page 794: ...Appendix B ADC Electricals S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 794 Freescale Semiconductor...

Page 795: ...th no abrupt changes in the VCOCLK frequency Noise voltage temperature and other factors cause slight variations in the control loop resulting in a clock jitter This jitter affects the real minimum an...

Page 796: ...VDDX 5 5 V junction temperature from 40 C to 150 C unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 D VCO frequency during system reset fVCORST 8 32 MHz 2 C VCO locking range fVCO 32 64...

Page 797: ...e Semiconductor 797 Appendix D IRC Electrical Specifications Table D 1 IRC electrical characteristics Num C Rating Symbol Min Typ Max Unit 1 P Junction Temperature 40 to 150 Celsius Internal Reference...

Page 798: ...Appendix D IRC Electrical Specifications S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 798 Freescale Semiconductor...

Page 799: ...e target output voltage which can be 1 3 1 2 or 2 3 VLCD After a positive spike on VBuf a frontplane or backplane is discharged by an active load with a constant current After a negative spike on VBuf...

Page 800: ...is shown in Figure E 3 The resistive output characteristic is also valid if an output is forced to GND or VLCD Figure E 2 VBuf transients not to scale Figure E 3 buffer output characteristic VBuf t 2...

Page 801: ...ctrical Specifications F 1 MSCAN Electrical Characteristics Table F 1 MSCAN Wake up Pulse Characteristics Conditions are shown in Table F 1 unless otherwise noted Num C Rating Symbol Min Typ Max Unit...

Page 802: ...Appendix F MSCAN Electrical Specifications S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 802 Freescale Semiconductor...

Page 803: ...Timing Characteristics 32 MHz 64KB PFlash 2KB EEPROM Num Command fNVMOP cycle fNVMBUS cycle Symbol Min 1 Typ 2 Max 3 Worst 4 Unit 1 Erase Verify All Blocks4 5 0 34528 tRD1ALL 1 08 1 08 2 16 69 06 ms...

Page 804: ...P and typical fNVMBUS plus aging 4 Worst times are based on minimum fNVMOP and minimum fNVMBUS plus aging 5 Affected by Pflash size 6 Affected by EEPROM size Table G 2 NVM Reliability Characteristics...

Page 805: ...ogy measured at high temperature and de rated to 25 C using the Arrhenius equation For additional information on how Freescale defines Typical Data Retention please refer to Engineering Bulletin EB618...

Page 806: ...Appendix G NVM Electrical Parameters S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 806 Freescale Semiconductor...

Page 807: ...Sense module H 1 Maximum Ratings Table H 1 Maximum ratings of the Supply Voltage Sense BATS Characteristics noted under conditions 5 5V VSUP 18 V 40 C TJ 150 C 1 unless otherwise noted Typical values...

Page 808: ...edge Deassert Measured on selected pin rising edge Hysteresis measured on selected pin VLBI3_A VLBI3_D VLBI3_H 7 7 75 0 4 8 5 9 V V V 4 P Low Voltage Warning LBI 4 Assert Measured on selected pin fal...

Page 809: ...lectrical Characteristics Supply Voltage Sense BATS Characteristics noted under conditions 5 5V VSUP 18 V 40 C TJ 150 C 1 unless otherwise noted Typical values noted reflect the approximate parameter...

Page 810: ...Appendix H BATS Electrical Specifications S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 810 Freescale Semiconductor...

Page 811: ...de stopmode VSUP 3 5V VDDX 4 85 4 50 3 13 2 5 5 0 5 0 5 5 5 15 5 25 5 25 5 75 V V V V 3 P Load Current VDDX 1 2 3 without external PNP Full Performance Mode VSUP 6V Full Performance Mode 3 5V VSUP 6V...

Page 812: ...the given maximum load currents and VSUP input voltages the MCU will stay out of reset 2 Load current without the use of external PNP transistor 3 Please note that the core current is derived from VDD...

Page 813: ...z 1 tUPOSC 1 6 8 ms 3c C Oscillator start up time 16MHz 1 tUPOSC 1 5 ms 3d C Oscillator start up time 20MHz 1 tUPOSC 1 4 ms 4 P Clock Monitor Failure Assert Frequency fCMFA 200 450 1200 kHz 5 D Input...

Page 814: ...Appendix J Electrical Characteristics for the Oscillator OSCLCPcr S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 814 Freescale Semiconductor...

Page 815: ...ext 10 3 32K_EXTAL Load Capacitance 32K_XTAL Load Capacitance Cx Cy 1 1 See crystal or resonator manufacturer s recommendation 4 External Feedback resistor RF 10 M 5 External Series resistor RS 200 K...

Page 816: ...Appendix K OSC32K Electrical Specifications S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 816 Freescale Semiconductor...

Page 817: ...SPI Master Timing CPHA 0 In Figure L 2 the timing diagram for master mode with transmission format CPHA 1 is depicted Table L 1 Measurement Conditions Description Value Unit Drive mode full drive mode...

Page 818: ...e Lead Time tlead 1 2 tsck 3 D Enable Lag Time tlag 1 2 tsck 4 D Clock SCK High or Low Time twsck 1 2 tsck 5 D Data Setup Time Inputs tsu 8 ns 6 D Data Hold Time Inputs thi 8 ns 9 D Data Valid after S...

Page 819: ...m fSCK to fbus ratio in Master Mode In Master Mode the allowed maximum fSCK to fbus ratio minimum Baud Rate Divisor pls see SPI Block Guide derates with increasing fbus please see Figure L 3 L 2 Slave...

Page 820: ...1 is depicted Figure L 5 SPI Slave Timing CPHA 1 SCK INPUT SCK INPUT MOSI INPUT MISO OUTPUT SS INPUT 1 9 5 6 MSB IN BIT 6 1 LSB IN SLAVE MSB SLAVE LSB OUT BIT 6 1 11 4 4 2 7 CPOL 0 CPOL 1 3 13 NOTE N...

Page 821: ...able Lead Time tlead 4 tbus 3 D Enable Lag Time tlag 4 tbus 4 D Clock SCK High or Low Time twsck 4 tbus 5 D Data Setup Time Inputs tsu 8 ns 6 D Data Hold Time Inputs thi 8 ns 7 D Slave Access Time tim...

Page 822: ...Appendix L SPI Electrical Specifications S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 822 Freescale Semiconductor...

Page 823: ...Symbol Min Typ Max Unit 1 C VLINSUP range VLINSUP_LIN 71 12 18 V 2 M Current limitation into the LIN pin in dominant state 3 VLIN VLINSUP_LIN_MAX ILIN_LIM 40 200 mA 3 M Input leakage current in domin...

Page 824: ...5 C under nominal conditions unless otherwise noted Num C Ratings Symbol Min Typ Max Unit 1 P Minimum duration of wake up pulse generating a wake up interrupt tWUFR 56 72 120 s 2 P TxD dominant timeou...

Page 825: ...c max 2 x tBit D4 0 590 LIN PHYSICAL LAYER DRIVER CHARACTERISTICS FOR FAST MODE SLEW RATE 100KBIT S UP TO 250KBIT S 13 T Rising falling edge time min to max max to min trise 0 5 s 14 T Over current ma...

Page 826: ...Appendix M LINPHY Electrical Specifications S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 826 Freescale Semiconductor...

Page 827: ...mber NOTE The mask identifier suffix and the Tape Reel suffix are always both omitted from the partnumber which is actually marked on the device For specific partnumbers to order please contact your l...

Page 828: ...Appendix O Package Information S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 829 Appendix O Package Information...

Page 829: ...Appendix O Package Information S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 830 Freescale Semiconductor O 1 144 LQFP...

Page 830: ...Appendix O Package Information S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 831...

Page 831: ...Appendix O Package Information S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 832 Freescale Semiconductor...

Page 832: ...Appendix O Package Information S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 833 O 2 100 LQFP...

Page 833: ...Appendix O Package Information S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 834 Freescale Semiconductor...

Page 834: ...Appendix O Package Information S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 Freescale Semiconductor 835...

Page 835: ...Appendix O Package Information S12ZVHY S12ZVHL Family Reference Manual Rev 1 05 836 Freescale Semiconductor...

Page 836: ...mber Revision Date Description of Changes Rev 0 01 08 Mar 2012 Initial Version Rev 0 02 19 Mar 2012 Update for CPMU register change Rev 0 03 19 April 2012 Update for RTC register change Rev 0 04 25 Ma...

Page 837: ...6 INT_XGPRIO R 0 0 0 0 0 XILVL 2 0 W 0x0017 INT_CFADDR R 0 INT_CFADDR 6 3 0 0 0 W 0x0018 INT_CFDATA0 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x0019 INT_CFDATA1 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x001A INT_CFDATA2 R R...

Page 838: ...0 0 0 0 0 0 W 0x0083 MMCCCRL R 0 CPUX 0 CPUI 0 0 0 0 W 0x0084 Reserved R 0 0 0 0 0 0 0 0 W 0x0085 MMCPCH R CPUPC 23 16 W 0x0086 MMCPCM R CPUPC 15 8 W 0x0087 MMCPCL R CPUPC 7 0 W 0x0088 0x00FF Reserved...

Page 839: ...TRIGF 0 EEVF ME3 ME2 ME1 ME0 W 0x010B DBGSR R TBF 0 0 PTACT 0 SSF2 SSF1 SSF0 W 0x010C 0x010F Reserved R 0 0 0 0 0 0 0 0 W 0x0110 DBGACTL R 0 NDB INST 0 RW RWE reserved COMPE W 0x0111 0x0114 Reserved...

Page 840: ...DBGBAL R DBGBA 7 0 W 0x0128 0x012F Reserved R 0 0 0 0 0 0 0 0 W 0x0130 DBGCCTL R 0 NDB INST 0 RW RWE reserved COMPE W 0x0131 0x0134 Reserved R 0 0 0 0 0 0 0 0 W 0x0135 DBGCAH R DBGCA 23 16 W 0x0136 DB...

Page 841: ...W 0x0148 0x017F Reserved R 0 0 0 0 0 0 0 0 W 0x0180 0x01FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0180 0x01FF Reserved R 0 0 0 0 0 0 0 0 W 0x0200 0x037F Port Integrati...

Page 842: ...0x0220 PTA R PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 W 0x0221 PTB R 0 0 0 0 PTB3 PTB2 PTB1 PTB0 W 0x0222 PTIA R PTIA7 PTIA6 PTIA5 PTIA4 PTIA3 PTIA2 PTIA1 PTIA0 W 0x0223 PTIB R 0 0 0 0 PTIB3 PTIB2 PTIB...

Page 843: ...D4 DDRD3 DDRD2 DDRD1 DDRD0 W 0x0246 PERC R PERC7 PERC6 PERC5 PERC4 PERC3 PERC2 PERC1 PERC0 W 0x0247 PERD R PERD7 PERD6 PERD5 PERD4 PERD3 PERD2 PERD1 PERD0 W 0x0248 PPSC R PPSC7 PPSC6 PPSC5 PPSC4 PPSC3...

Page 844: ...PTADL0 W 0x0282 Reserved R 0 0 0 0 0 0 0 0 W 0x0283 PTIADL R PTIADL7 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0 W 0x0284 Reserved R 0 0 0 0 0 0 0 0 W 0x0285 DDRADL R DDRADL7 DDRADL6 DDRA...

Page 845: ...3 PTIT2 PTIT1 PTIT0 W 0x02C2 DDRT R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W 0x02C3 PERT R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W 0x02C4 PPST R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2...

Page 846: ...0 PTP R PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W 0x02F1 PTIP R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 W 0x02F2 DDRP R DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 W 0x02F3 PERP R PERP7 PE...

Page 847: ...TG3 PTG2 PTG1 PTG0 W 0x0321 PTIG R PTIG7 PTIG6 PTIG5 PTIG4 PTIG3 PTIG2 PTIG1 PTIG0 W 0x0322 DDRG R DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0 W 0x0323 PERG R PERG7 PERG6 PERG5 PERG4 PERG3 PERG2 P...

Page 848: ...FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W 0x0381 FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 W 0x0382 FCCOBIX R 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 W 0x0383 FPSTAT R FPOVRD 0 0 0 0 0 0 WSTATAC K W 0x...

Page 849: ...OB2LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0392 FCCOB3HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0393 FCCOB3LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W...

Page 850: ...SBEEIE W 0x03C2 ECCIF R 0 0 0 0 0 0 0 SBEEIF W 0x03C3 0x03C6 Reserved R 0 0 0 0 0 0 0 0 W 0x03C7 ECCDPTRH R DPTR 23 16 W 0x03C8 ECCDPTRM R DPTR 15 8 W 0x03C9 ECCDPTRL R DPTR 7 1 0 W 0x03CA 0x3CB Rese...

Page 851: ...0x0405 TIM1TCNTL R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W 0x0406 TIM1TSCR1 R TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 W 0x0407 TIM1TTOV R TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 W 0x0408 TIM1TCTL1...

Page 852: ...042D Reserved R W 0x042E TIM1PTPSR R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 W 0x042F Reserved R W 0x0430 0x047F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0430 0x...

Page 853: ...2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x048D PWMCNT1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x048E PWMCNT2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x048F PWMCNT3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0...

Page 854: ...6 5 4 3 2 1 Bit 0 W 0x049F PWMDTY3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x04A0 PWMDTY4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x04A1 PWMDTY5 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x04A2 PWMDTY6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x04A3...

Page 855: ...TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 W 0x05C8 TIM0TCTL1 R OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 W 0x05C9 TIM0TCTL2 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 W 0x05CA TIM0TCTL3 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A E...

Page 856: ...R W 0x05F0 0x05FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x05F0 0x05FF Reserved R 0 0 0 0 0 0 0 0 W 0x0600 0x063F Analog to Digital Converter ADC Address Name Bit 7 Bit...

Page 857: ...W 0x060C ADC0CO NIF_0 R CON_IF 15 8 W 0x060D ADC0CO NIF_1 R CON_IF 7 1 EOL_IF W 0x060E ADC0IMDRI_0 R CSL_IMD RVL_IMD 0 0 0 0 0 0 0x060F ADC0IMDRI_1 R 0 RIDX_IMD W 0x0610 ADC0EOLRI R CSL_EOL RVL_EOL 0...

Page 858: ...E ADC0CBP_1 R CMD_PTR 15 8 W 0x061F ADC0CBP_2 R CMD_PTR 7 2 0 0 W 0x0620 ADC0RIDX R 0 0 RES_IDX 5 0 W 0x0621 ADC0RBP_0 R 0 0 0 0 RES_PTR 19 16 W 0x0622 ADC0RBP_1 R RES_PTR 15 8 W 0x0623 ADC0RBP_2 R RE...

Page 859: ...0 0 0 0 0 0 W 0x06C2 CPMU RESERVED02 R 0 0 0 0 0 0 0 0 W 0x06C3 CPMURFLG R 0 PORF LVRF 0 COPRF 0 OMRF PMRF W 0x06C4 CPMU SYNR R VCOFRQ 1 0 SYNDIV 5 0 W 0x06C5 CPMU REFDIV R REFFRQ 1 0 0 0 REFDIV 3 0...

Page 860: ...APIRH R APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W 0x06D5 CPMUAPIRL R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W 0x06D6 RESERVED CPMUTEST3 R 0 0 0 0 0 0 0 0 W 0x06D7 CPMUHTTR R HTO...

Page 861: ...2 BATIE R 0 0 0 0 0 0 BVHIE BVLIE W 0x06F3 BATIF R 0 0 0 0 0 0 BVHIF BVLIF W 0x06F4 0x06F5 Reserved R 0 0 0 0 0 0 0 0 W 0x06F8 0x06FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi...

Page 862: ...essible if the AMAP bit in the SCI0SR2 register is set to one 0x0708 0x070F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0708 0x070F Reserved R 0 0 0 0 0 0 0 0 W 0x0710 0x07...

Page 863: ...is set to one 0x0718 0x077F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0718 0x077F Reserved R 0 0 0 0 0 0 0 0 W 0x0780 0x0787 Serial Peripheral Interface SPI0 Address Nam...

Page 864: ...0 0x07C0 IIC0IBAD R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0 W 0x07C1 IIC0IBFD R IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 W 0x07C2 IIC0IBCR R IBEN IBIE MS SL TX RX TXAK 0 0 IBSWAI W RSTA 0x07C3 IIC0IBSR R...

Page 865: ...IF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF W 0x0805 CAN0RIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0806 CAN0TFLG R 0 0 0 0 0 TXE2 TXE1 TXE0 W 0x0807 CAN0TIER R 0 0 0 0 0 TXEIE2 T...

Page 866: ...Reserved R 0 0 0 0 0 0 0 0 W 0x0900 0x0987 LIN Physical Layer 0 LINPHY0 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0980 LP0DR R 0 0 0 0 0 0 LPDR1 LPDR0 W 0x0981 LP0CR R 0 0 0 0 LPE...

Page 867: ...FP13EN FP12EN FP11EN FP10EN FP9EN FP8EN W 0x0A04 LCDFPENR2 R FP23EN FP22EN FP21EN FP20EN FP19EN FP18EN FP17EN FP16EN W 0x0A05 LCDFPENR3 R FP31EN FP30EN FP29EN FP28EN FP27EN FP26EN FP25EN FP24EN W 0x0A...

Page 868: ...2 FP25BP1 FP25BP0 FP24BP3 FP24BP2 FP24BP1 FP24BP0 W 0x0A15 LCDRAM13 R FP27BP3 FP27BP2 FP27BP1 FP27BP0 FP26BP3 FP26BP2 FP26BP1 FP26BP0 W 0x0A16 LCDRAM14 R FP29BP3 FP29BP2 FP29BP1 FP29BP0 FP28BP3 FP28BP...

Page 869: ...P1 P0 W 0x0A44 0x0A4F Reserved R 0 0 0 0 0 0 0 0 W 0x0A50 MCCC0 R MCOM1 MCOM0 MCAM1 MCAM0 0 0 CD1 CD0 W 0x0A51 MCCC1 R MCOM1 MCOM0 MCAM1 MCAM0 0 0 CD1 CD0 W 0x0A52 MCCC2 R MCOM1 MCOM0 MCAM1 MCAM0 0 0...

Page 870: ...OVIE W FLMC 0x0A82 SSD0CTL R RTZE SDCPU SSDWAI FTST 0 0 ACLKS W 0x0A83 SSD0FLG R MCZIF 0 0 0 0 0 0 AOVIF W 0x0A84 MDC0CNTH R MDCCNT 15 8 W 0x0A85 MDC0CNTL R MDCCNT 7 0 W 0x0A86 ITG0ACCH R ITGACC 15 8...

Page 871: ...e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0A98 0x0ADF Reserved R 0 0 0 0 0 0 0 0 W 0x0AE0 0x0AEF Real Time Clock RTC Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0AE0 RTCCT...

Page 872: ...t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0AF0 0x0AFF Reserved R 0 0 0 0 0 0 0 0 W 0x0B00 0x0B17 Simple Sound Generator SSG0 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0B00 SSG0CR R SSGE...

Page 873: ...DUR4 DUR3 DUR2 DUR1 DUR0 W 0x0B0D SSG0IE R 0 0 0 0 0 0 0 RNDIE W 0xC0E SSG0IF R 0 0 0 0 0 0 0 RNDI W 0x0B0F RESERVED R 0 0 0 0 0 0 0 0 W 0x0B10 SSG0AMPBH R 0 0 0 0 0 AMPB10 AMPB9 AMPB8 W 0x0B11 SSG0A...

Page 874: ...on consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary...

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