Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
216 Freescale Semiconductor
Table 6-48. Normal and Loop1 Mode Trace Buffer Format with Timestamp
CINF contains information relating to the CPU.
CPU Information Byte CINF For Normal And Loop1 Modes
CPU CINF1 CPCH1 CPCM1 CPCL1 CINF0 CPCH0 CPCM0 CPCL0
CINF3 CPCH3 CPCM3 CPCL3 CINF2 CPCH2 CPCM2 CPCL2
Mode
8-Byte Wide Trace Buffer Line
7 6 5 4 3 2 1 0
CPU Timestamp Timestamp Reserved Reserved CINF0 CPCH0 CPCM0 CPCL0
Timestamp Timestamp Reserved Reserved CINF1 CPCH1 CPCM1 CPCL1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CET 0 0 CTI EEVI 0 TOVF
Figure 6-27. CPU Information Byte CINF
Table 6-49. CINF Bit Descriptions
Field Description
7–6
CET
CPU Entry Type Field — Indicates the type of stored address of the trace buffer entry as described in Table 6-50
3
CTI
Comparator Timestamp Indicator — This bit indicates if the trace buffer entry corresponds to a comparator
timestamp.
0 Trace buffer entry initiated by trace mode specification conditions or timestamp counter overflow
1 Trace buffer entry initiated by comparator D match
2
EEVI
External Event Indicator — This bit indicates if the trace buffer entry corresponds to an external event.
0 Trace buffer entry not initiated by an external event
1 Trace buffer entry initiated by an external event
0
TOVF
Timestamp Overflow Indicator — Indicates if the trace buffer entry corresponds to a timestamp overflow
0 Trace buffer entry not initiated by a timestamp overflow
1 Trace buffer entry initiated by a timestamp overflow
Table 6-50. CET Encoding
CET Entry Type Description
00 Non COF opcode address (entry forced by an external event)
01 Vector destination address
10 Source address of COF opcode
11 Destination address of COF opcode
Table 6-47. Normal and Loop1 Mode Trace Buffer Format without Timestamp