Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
188
Freescale Semiconductor
6.3.2.3
Debug Trace Control Register High (DBGTCRH)
Read: Anytime.
Write: Anytime the module is disarmed and PTACT is clear.
WARNING
DBGTCR[7] is reserved. Setting this bit maps the tracing to an unimplemented bus, thus
preventing proper operation.
This register configures the trace buffer for tracing and profiling.
Address: 0x0102
7
6
5
4
3
2
1
0
R
reserved
TSOURCE
TRANGE
TRCMOD
TALIGN
W
Reset
0
0
0
0
0
0
0
0
Figure 6-5. Debug Trace Control Register (DBGTCRH)
Table 6-8. DBGTCRH Field Descriptions
Field
Description
6
TSOURCE
Trace Control Bits
— The TSOURCE enables the tracing session.
0 No CPU tracing/profiling selected
1 CPU tracing/profiling selected
5–4
TRANGE
Trace Range Bits
— The TRANGE bits allow filtering of trace information from a selected address range when
tracing from the CPU in Detail mode. These bits have no effect in other tracing modes. To use a comparator for
range filtering, the corresponding COMPE bit must remain cleared. If the COMPE bit is set then the comparator
is used to generate events and the TRANGE bits have no effect. See
for range boundary definition.
3–2
TRCMOD
Trace Mode Bits
— See
for detailed Trace Mode descriptions. In Normal Mode, change of flow
information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See
1–0
TALIGN
Trigger Align Bits
— These bits control whether the trigger is aligned to the beginning, end or the middle of a
tracing or profiling session. See
Table 6-9. TRANGE Trace Range Encoding
TRANGE Tracing
Range
00
Trace from all addresses (No filter)
01
Trace only in address range from $00000 to Comparator D
10
Trace only in address range from Comparator C to $FFFFFF
11
Trace only in range from Comparator C to Comparator D
Table 6-10. TRCMOD Trace Mode Bit Encoding
TRCMOD
Description
00
Normal
01
Loop1
