Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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Freescale Semiconductor
5.1.2
Features
The BDC includes these distinctive features:
•
Single-wire communication with host development system
•
SYNC command to determine communication rate
•
Genuine non-intrusive handshake protocol
•
Enhanced handshake protocol for error detection and stop mode recognition
•
Active out of reset in special single chip mode
•
Most commands not requiring active BDM, for minimal CPU intervention
•
Full global memory map access without paging
•
Simple flash mass erase capability
5.1.3
Modes of Operation
S12 devices feature power modes (run, wait, and stop) and operating modes (normal single chip, special
single chip). Furthermore, the operation of the BDC is dependent on the device security status.
5.1.3.1
BDC Modes
The BDC features module specific modes, namely disabled, enabled and active. These modes are
dependent on the device security and operating mode. In active BDM the CPU ceases execution, to allow
BDC system access to all internal resources including CPU internal registers.
5.1.3.2
Security and Operating mode Dependency
In device run mode the BDC dependency is as follows
•
Normal modes, unsecure device
General BDC operation available. The BDC is disabled out of reset.
•
Normal modes, secure device
BDC disabled. No BDC access possible.
•
Special single chip mode, unsecure
BDM active out of reset. All BDC commands are available.
•
Special single chip mode, secure
BDM active out of reset. Restricted command set available.
When operating in secure mode, BDC operation is restricted to allow checking and clearing security by
mass erasing the on-chip flash memory. Secure operation prevents BDC access to on-chip memory other
than mass erase. The BDC command set is restricted to those commands classified as Always-available.
