Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 153
If the ACK pulse handshake protocol is enabled and STEAL is cleared, then the BDC waits for the first
free bus cycle to make a non-intrusive access. If no free bus cycle occurs within 512 core clock cycles then
the BDC aborts the access, sets the NORESP bit and uses a long ACK pulse to indicate an error condition
to the host.
Table 5-8 summarizes the BDC command set. The subsequent sections describe each command in detail
and illustrate the command structure in a series of packets, each consisting of eight bit times starting with
a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The
time for an 8-bit command is 8

16 target BDCSI clock cycles.
The nomenclature below is used to describe the structure of the BDC commands. Commands begin with
an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first)
/ = separates parts of the command
d = delay 16 target BDCSI clock cycles (DLY)
dack = delay (16 cycles) no ACK; or delay (=> 32 cycles) then ACK.(DACK)
ad24 = 24-bit memory address in the host-to-target direction
rd8 = 8 bits of read data in the target-to-host direction
rd16 = 16 bits of read data in the target-to-host direction
rd24 = 24 bits of read data in the target-to-host direction
rd32 = 32 bits of read data in the target-to-host direction
rd64 = 64 bits of read data in the target-to-host direction
rd.sz = read data, size defined by sz, in the target-to-host direction
wd8 = 8 bits of write data in the host-to-target direction
wd16 = 16 bits of write data in the host-to-target direction
wd32 = 32 bits of write data in the host-to-target direction
wd.sz = write data, size defined by sz, in the host-to-target direction
ss = the contents of BDCCSRL in the target-to-host direction
sz = memory operand size (00 = byte, 01 = word, 10 = long)
(sz = 11 is reserved and currently defaults to long)
crn = core register number, 32-bit data width
WS = command suffix signaling the operation is with status
Table 5-8. BDC Command Summary
Command
Mnemonic
Command
Classification
ACK
Command
Structure
Description
SYNC Always
Available
N/A N/A
(1)
Request a timed reference pulse to
determine the target BDC communication
speed
ACK_DISABLE Always
Available
No 0x03/d Disable the communication handshake.
This command does not issue an ACK
pulse.
ACK_ENABLE Always
Available
Yes 0x02/dack Enable the communication handshake.
Issues an ACK pulse after the command is
executed.
BACKGROUND Non-Intrusive Yes 0x04/dack Halt the CPU if ENBDC is set. Otherwise,
ignore as illegal command.