Chapter 18 Real-Time Counter With Calendar (RTCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
647
18.4.6 RTC Compensation Configure Register (RTCCCR)
This register includes the CCS and Q value for free run 16-bit counter match times with M and M+1
modulo value during compensation.See compensation function section for detail.
18.4.7 RTC Counter Register (RTCCNT)
RTCCNT is the read-only value of the current RTC count of the 16-bit counter.
2
COMPF
Compensation cycle Flag
— This status bit is set on every last second of compensation cycle. When the
COMPIE bit is set, COMPF generates a CPU interrupt request. Writing a logic 0 has no effect. Writing a logic 1
clears the bit and the time base interrupt request. Reset clears COMPF to 0.
0 No Compensation cycle has occurred.
1 A compensation cycle has occurred.
0
TB0F
4 Hz time tick Flag
— This status bit is set on every 4 Hz time ticket. When the TB0IE bit is set, TB0F generates
a CPU interrupt request. Writing a logic 0 has no effect. Writing a logic 1 clears the bit and the time base interrupt
request. Reset clears TB0F to 0.
0 No 4 Hz time tick has occurred.
1 A 4 Hz time tick has occurred.
7
6
5
4
3
2
1
0
R
CCS
Q
W
POR:
0
0
0
0
0
0
0
0
Figure 18-7. RTC Compensation Configure Register (RTCCCR)
Table 18-8. RTCCCR Field Descriptions
Field
Description
7:6
CCS
Compensation cycle selection
— When the clock compensation mechanism enabled, It will decide the
compensation cycle.
00 -- 5 second compensation cycle
01 -- 15 second compensation cycle
10 -- 30 second compensation cycle
11 -- 60 second compensation cycle
5:0
Q
16-bit Counter Matches with M+1 Modulo Value Times
— When the clock compensation mechanism
enabled, the free run timer counter matches with M+1 modulo value which set in RTC modulo register
(RTCMOD) Q times first, then matches with M modulo value with reset compensation cycle time. When Q is 0,
free run timer counter matches with M+1 modulo value do not happen. Refer to
Section Table 18-14., “the CCS,
15
14
13
12
11
10
9
8
R
RTCCNTH
W
POR:
0
0
0
0
0
0
0
0
Table 18-7. RTCS1 Field Descriptions (continued)
Field
Description
