Chapter 19 Simple Sound Generator (SSGV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
665
19.3.2.8
SSG Tone Duration register (SSGDUR)
The SSGDUR register defines the number of tone cycle in one tone duration. The tone cycle number in
one duration is 1.
Read: Anytime
Write: Anytime
19.3.2.9
SSG Interrupt Enable (SSGIE)
The SSGIE controls the enable of the interrupt.
Table 19-10. SSGAT Field Descriptions
Field
Description
10–0
AT[10:0]
SSG Amplitude Threshold Register Bits —
When the amplitude >= SSGAT (attack) or amplitude <=SSGAT (decay), an interrupt will be triggered.
Module Base + 0x000C
7
6
5
4
3
2
1
0
R
DUR7
DUR6
DUR5
DUR4
DUR3
DUR2
DUR1
DUR0
W
Reset
0
0
0
0
0
0
0
0
Figure 19-15. SSG Tone Duration Register (SSGDUR)
Table 19-11. SSGDUR Field Descriptions
Field
Description
7–0
DUR[7:0]
SSG Tone Duration Register bits —
These bits defines the number of tone cycle. The tone number in one duration is 1.
In attack/decay mode, when tone duration counter reach the 1, amplitude will increase/decrease by
SSGAA.
In non-attack/decay mode, when tone duration counter reach the 1, config registers will reload if
RDR of SSGCR is 1, or SSG will stop if RDR of SSGCR is 0.
Module Base + 0x000D
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
RNDIE
W
Reset
0
0
0
0
0
0
0
0
Figure 19-16. SSG Interrupt Enable Register (SSGIE)
