Freescale Semiconductor MC9S12ZVHL32, Reference Manual

Page: 171 / 874

Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 171
The BDC serial interface uses a clocking scheme in which the external host generates a falling edge on the
BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if during a command 512 clock cycles occur between falling edges from the
host. The timeout forces the current command to be discarded.
The BKGD pin is a pseudo open-drain pin and has a weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief drive-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
The timing for host-to-target is shown in Figure 5-6 and that of target-to-host in Figure 5-7 and
Figure 5-8 . All cases begin when the host drives the BKGD pin low to generate a falling edge. Since the
host and target operate from separate clocks, it can take the target up to one full clock cycle to recognize
this edge; this synchronization uncertainty is illustrated in
Figure 5-6 . The target measures delays from this
perceived start of the bit time while the host measures delays from the point it actually drove BKGD low
to start the bit up to one target clock cycle earlier. Synchronization between the host and target is
established in this manner at the start of every bit time.
Figure 5-6 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later than eight target clock cycles after the falling edge for a logic 1
transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven
signals.
Figure 5-6. BDC Host-to-Target Serial Bit Timing
Figure 5-7 shows the host receiving a logic 1 from the target system. The host holds the BKGD pin low
long enough for the target to recognize it (at least two target clock cycles). The host must release the low
EARLIEST START
TARGET SENSES BIT LEVEL
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
BDCSI clock
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED START
OF BIT TIME
OF NEXT BIT