Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
173
Figure 5-8. BDC Target-to-Host Serial Bit Timing (Logic 0)
5.4.7
Serial Interface Hardware Handshake (ACK Pulse) Protocol
BDC commands are processed internally at the device core clock rate. Since the BDCSI clock can be
asynchronous relative to the bus frequency, a handshake protocol is provided so the host can determine
when an issued command has been executed. This section describes the hardware handshake protocol.
The hardware handshake protocol signals to the host controller when a BDC command has been executed
by the target. This protocol is implemented by a low pulse (16 BDCSI clock cycles) followed by a brief
speedup pulse on the BKGD pin, generated by the target MCU when a command, issued by the host, has
been successfully executed (see
). This pulse is referred to as the ACK pulse. After the ACK
pulse has finished, the host can start the bit retrieval if the last issued command was a read command, or
start a new command if the last command was a write command or a control command.
Figure 5-9. Target Acknowledge Pulse (ACK)
10 CYCLES
BDCSI clock
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TARGET MCU
DRIVE AND
PERCEIVED START
OF BIT TIME
HIGH-IMPEDANCE
BKGD PIN
10 CYCLES
SPEED-UP PULSE
SPEEDUP
PULSE
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
16 CYCLES
BDCSI clock
(TARGET MCU)
TARGET
TRANSMITS
HIGH-IMPEDANCE
BKGD PIN
HIGH-IMPEDANCE
MINIMUM DELAY
FROM THE BDC COMMAND
32 CYCLES
EARLIEST
START OF
NEXT BIT
SPEED UP PULSE
16th CYCLE OF THE
LAST COMMAND BIT
ACK PULSE
