Chapter 16 Motor Controller (MC10B8CV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
607
The following sequence should be used to update the current magnitude and direction for coil 0 and coil 1
of the motor to achieve consistent PWM output:
1. Write to duty cycle register x
2. Write to duty cycle register x + 1.
At the next timer counter overflow, the duty cycle registers will be copied to the working duty cycle
registers. Sequential writes to the duty cycle register x will result in the previous data being overwritten.
16.4.1.1.2
Full H-Bridge Mode (MCOM = 10)
In full H-bridge mode, the PWM channels x and x + 1 operate independently. The duty cycle working
registers are updated whenever a timer counter overflow occurs.
16.4.1.1.3
Half H-Bridge Mode (MCOM = 00 or 01)
In half H-bridge mode, the PWM channels x and x + 1 operate independently. In this mode, each PWM
channel can be configured such that one pin is released and the other pin is a PWM output.
shows a typical configuration in half H-bridge mode.
The two pins associated with each channel are switchable between released mode and PWM output
dependent upon the state of the MCOM[1:0] bits in the MCCCx (channel control) register. See register
description in
Section 16.3.2.4, “Motor Controller Channel Control Registers”
. In half H-bridge mode, the
state of the S bit has no effect.
Figure 16-11. Typical Quad Half H-Bridge Mode Configuration
PWM Channel x
PWM Channel x + 1
MnC0P
MnC0M
MnC1P
MnC1M
Released
PWM Output
V
SSM
V
DDM
V
SSM
V
DDM
Released
PWM Output
