Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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Freescale Semiconductor
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When a reset occurs the debugger pulls BKGD low until the reset ends, forcing SSC mode entry.
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Then the debugger reads the reset flags to determine the cause of reset.
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If required, the debugger can read the trace buffer to see what happened just before reset. Since the
trace buffer and DBGCNT register are not affected by resets other than POR.
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The debugger configures and arms the DBG to start tracing on returning to application code.
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The debugger then sets the PC according to the reset flags.
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Then the debugger returns to user code with GO or STEP1.
6.5.3
Breakpoints from other S12Z sources
The DBG is neither affected by CPU BGND instructions, nor by BDC BACKGROUND commands.
6.5.4
Code Profiling
The code profiling data output pin PDO is mapped to a device pin that can also be used as GPIO in an
application. If profiling is required and all pins are required in the application, it is recommended to use
the device pin for a simple output function in the application, without feedback to the chip. In this way the
application can still be profiled, since the pin has no effect on code flow.
The PDO provides a simple bit stream that must be strobed at both edges of the profiling clock when
profiling. The external development tool activates profiling by setting the DBG ARM bit, with PROFILE
and PDOE already set. Thereafter the first bit of the profiling bit stream is valid at the first rising edge of
the profiling clock. No start bit is provided. The external development tool must detect this first rising edge
after arming the DBG. To detect the end of profiling, the DBG ARM bit can be monitored using the BDC.
