Chapter 23 LIN Physical Layer (S12LINPHYV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
762
Freescale Semiconductor
23.3.2.6
LIN Status Register (LPSR)
Module Base + Address 0x0005
Access: User read/write
(1)
1. Read: Anytime
Write: Never, writes to this register have no effect
7
6
5
4
3
2
1
0
R
LPDT
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented
Figure 23-8. LIN Status Register (LPSR)
Table 23-7. LPSR Field Description
Field
Description
7
LPDT
LIN Transmitter TxD-dominant timeout Status Bit
— This read-only bit signals that the LPTxD pin is still
dominant after a TxD-dominant timeout. As long as the LPTxD is dominant after the timeout the LIN transmitter
is shut down and the LPTDIF is set again after attempting to clear it.
0 If there was a TxD-dominant timeout, LPTxD has ceased to be dominant after the timeout.
1 LPTxD is still dominant after a TxD-dominant timeout.
