Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
146
Freescale Semiconductor
5.3.2
Register Descriptions
The BDC registers are shown in
. Registers are accessed only by host-driven communications
to the BDC hardware using READ_BDCCSR and WRITE_BDCCSR commands. They are not accessible
in the device memory map.
5.3.2.1
BDC Control Status Register High (BDCCSRH)
Figure 5-3. BDC Control Status Register High
(
BDCCSRH)
Read: All modes through BDC operation only.
Write: All modes through BDC operation only, when not secured, but subject to the following:
— Bits 7,3 and 2 can only be written by WRITE_BDCCSR commands.
— Bit 5 can only be written by WRITE_BDCCSR commands when the device is not in stop mode.
— Bits 6, 1 and 0 cannot be written. They can only be updated by internal hardware.
Global
Address
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
Not
Applicable
BDCCSRH R
ENBDC
BDMACT
BDCCIS
0
STEAL
CLKSW
UNSEC
ERASE
W
Not
Applicable
BDCCSRL R
WAIT
STOP
RAMWF
OVRUN
NORESP
RDINV
ILLACC
ILLCMD
W
= Unimplemented, Reserved
0
= Always read zero
Figure 5-2. BDC Register Summary
Register Address: This register is not in the device memory map. It is accessible using BDC inherent addressing commands
7
6
5
4
3
2
1
0
R
ENBDC
BDMACT
BDCCIS
0
STEAL
CLKSW
UNSEC
ERASE
W
Reset
Secure AND SSC-Mode
1
1
0
0
0
0
0
0
Unsecure AND SSC-Mode
1
1
0
0
0
0
1
0
Secure AND NSC-Mode
0
0
0
0
0
0
0
0
Unsecure AND NSC-Mode
0
0
0
0
0
0
1
0
= Unimplemented, Reserved
0
= Always read zero
