Chapter 1 Device Overview MC9S12ZVHY/MC9S12ZVHL Families
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
69
and comparing the result to the reference value in the IFR, it is possible to determine the ADC’s reference
voltage V
RH
in the application environment:
The exact absolute value of an analog conversion can be determined as follows:
With:
ConvertedADInput:
Result of the analog to digital conversion of the desired pin
ConvertedReference:
Result of channel “Internal_1” conversion
StoredReference:
Value in IFR location 0x1F_C040/0x1F_C041
n:
ADC resolution (10 bit)
1.17
BDC Clock Source Connectivity
The BDC clock, BDCCLK, is mapped to the IRCCLK generated in CPMU module. The BDC clock,
BDCFCLK, is mapped to the bus clock.
1.18
FTMRZ Connectivity
The soc_erase_all_req input to the flash module is driven directly by a BDC erase flash request resulting
from the BDC ERASE_FLASH command.
The FTMRZ FCLKDIV register is forced to 0x05 by the BDC ERASE_FLASH command. This
configures the clock frequency correctly for the initial bus frequency on leaving reset. The bus frequency
must not be changed before launching the ERASE_FLASH command.
1.19
RTC Clock Source
The RTC has three clock source, the 32K OSC, main OSC or IRC, refer to
for more information. When select main OSC, user need to config the registers
in CPMU block, refer to CPMU block guide for more detailed information. And main OSC will be stop if
silicon enter full stop mode. And if select the 1 MHz internal IRC clock, then the clock will be off when
enter full stop or pseudo stop mode, the RTC function will be stop.
V
RH
StoredReference
ConvertedReference
------------------------------------------------------- 5V
=
Result
ConvertedADInput
StoredReference 5V
ConvertedReference 2
n
------------------------------------------------------------------
=
