Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 4 Interrupt (S12ZINTV0)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
130 Freescale Semiconductor
Figure 4-1. INT Block Diagram
4.2 External Signal Description
The INT module has no external signals.
4.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the INT module.
4.3.1 Module Memory Map
Table 4-3 gives an overview over all INT module registers.
Table 4-3. INT Memory Map
Address Use Access
0x000010–0x000011 Interrupt Vector Base Register (IVBR) R/W
0x000012–0x000016 RESERVED —
0x000017 Interrupt Request Configuration Address Register
(INT_CFADDR)
R/W
0x000018 Interrupt Request Configuration Data Register 0
(INT_CFDATA0)
R/W
Wake Up
Current
IVBR
One Set Per Channel
Interrupt
Requests
Interrupt Requests
CPU
Vector
Address
New
IPL
IPL
(Up to 117 Channels)
PRIOLVLn Priority Level
= configuration bits from the associated
channel configuration register
IVBR = Interrupt Vector Base
IPL = Interrupt Processing Level
PRIOLVL0
PRIOLVL1
PRIOLVL2
Peripheral
To
C
P
U
Priority Decode
r
Non I Bit Maskable
Channels
Priority
Level
Filter
Highest Pending
IPL