Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
180
Freescale Semiconductor
6.1.2
Overview
The comparators monitor the bus activity of the CPU. A single comparator match or a series of matches
can trigger bus tracing and/or generate breakpoints. A state sequencer determines if the correct series of
matches occurs. Similarly an external event can trigger bus tracing and/or generate breakpoints.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads.
6.1.3
Features
•
Four comparators (A, B, C, and D)
— Comparators A and C compare the full address bus and full 32-bit data bus
— Comparators A and C feature a data bus mask register
— Comparators B and D compare the full address bus only
— Each comparator can be configured to monitor PC addresses or addresses of data accesses
— Each comparator can select either read or write access cycles
— Comparator matches can force state sequencer state transitions
•
Three comparator modes
— Simple address/data comparator match mode
— Inside address range mode, Addmin
Address
Addmax
— Outside address range match mode, Address
Addmin
or Address
Addmax
•
State sequencer control
— State transitions forced by comparator matches
— State transitions forced by software write to TRIG
— State transitions forced by an external event
•
The following types of breakpoints
— CPU breakpoint entering active BDM on breakpoint (BDM)
— CPU breakpoint executing SWI on breakpoint (SWI)
•
Trace control
BDM
Background Debug Mode.
In this mode CPU application code execution is halted.
Execution of BDC “active BDM” commands is possible.
BDC
Background Debug Controller
WORD
16-bit data entity
Data Line
64-bit data entity
CPU
S12Z CPU module
Trigger
A trace buffer input that triggers tracing start, end or mid point
Table 6-2. Glossary Of Terms
Term
Definition
