Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
Freescale Semiconductor
287
7.5.2
Description of Reset Operation
Upon detection of any reset of
, an internal circuit drives the RESET pin low for 512 PLLCLK
cycles. After 512 PLLCLK cycles the RESET pin is released. The internal reset of the MCU remains
asserted while the reset generator completes the 768 PLLCLK cycles long reset sequence.In case the
RESET pin is externally driven low for more than these 768 PLLCLK cycles (External Reset), the internal
reset remains asserted longer.
NOTE
While System Reset is asserted the PLLCLK runs with the frequency
f
VCORST
.
Figure 7-40. RESET Timing
7.5.3
Oscillator Clock Monitor Reset
If the external oscillator is enabled (OSCE=1)and the oscillator clock monitor reset is enabled (OMRE=1),
then in case of loss of oscillation or the oscillator frequency drops below the failure assert frequency f
CMFA
(see device electrical characteristics for values), the S12CPMU_UHV_V5 generates an Oscillator Clock
Monitor Reset. In Full Stop Mode the external oscillator and the oscillator clock monitor are disabled.
Oscillator Clock Monitor Reset
OSCE Bit in CPMUOSC register and
OMRE Bit in CPMUOSC2 register
COP Reset
CR[2:0] in CPMUCOP register
Table 7-34. Reset Summary
Reset Source
Local Enable
)
(
)
PLLCLK
512 cycles
256 cycles
S12_CPMU drives
possibly
RESET
driven low
externally
)
(
(
RESET
S12_CPMU releases
f
VCORST
RESET pin low
RESET pin
f
VCORST
