Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
201
6.3.2.18
Debug Comparator C Control Register (DBGCCTL)
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
shows the effect for RWE and RW on the comparison conditions. These bits are ignored if
INST is set, because matches based on opcodes reaching the execution stage are data independent.
Address: 0x0130
7
6
5
4
3
2
1
0
R
0
NDB
INST
0
RW
RWE
reserved
COMPE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-20. Debug Comparator C Control Register
Table 6-33. DBGCCTL Field Descriptions
Field
Description
6
NDB
Not Data Bus
— The NDB bit controls whether the match occurs when the data bus matches the comparator
register value or when the data bus differs from the register value. This bit is ignored if the INST bit in the
same register is set.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
5
INST
Instruction Select
— This bit configures the comparator to compare PC or data access addresses.
0 Comparator compares addresses of data accesses
1 Comparator compares PC address
3
RW
Read/Write Comparator Value Bit
— The RW bit controls whether read or write is used in compare for the
associated comparator. The RW bit is ignored if RWE is clear or INST is set.
0 Write cycle is matched
1 Read cycle is matched
2
RWE
Read/Write Enable Bit
— The RWE bit controls whether read or write comparison is enabled for the
associated comparator. This bit is not used if INST is set.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
0
COMPE
Enable Bit
— Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled
Table 6-34. Read or Write Comparison Logic Table
RWE Bit
RW Bit
RW Signal
Comment
0
x
0
RW not used in comparison
0
x
1
RW not used in comparison
1
0
0
Write match
1
0
1
No match
1
1
0
No match
