Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
181
— Tracing session triggered by state sequencer
— Begin, End, and Mid alignment of tracing to trigger
•
Four trace modes
— Normal: change of flow (COF) PC information is stored (see
) for change of
flow definition.
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all read/write access cycles are stored
— Pure PC: All program counter addresses are stored.
•
2 Pin (data and clock) profiling interface
— Output of code flow information
6.1.4
Modes of Operation
The DBG module can be used in all MCU functional modes.
The DBG module can issue breakpoint requests to force the device to enter active BDM or an SWI ISR.
The BDC BACKGROUND command is also handled by the DBG to force the device to enter active BDM.
When the device enters active BDM through a BACKGROUND command with the DBG module armed,
the DBG remains armed.
6.1.5
Block Diagram
B
Figure 6-1. Debug Module Block Diagram
CPU BUS
TRACE BUFFER
BUS INTERF
ACE
MATCH0
COMPARATOR B
COMPARATOR C
COMPARATOR D
COMPARATOR A
STATE SEQUENCER
MATCH1
MATCH2
MATCH3
TRACE
READ TRACE DATA (DBG READ DATA BUS)
CONTROL
BREAKPOINT
COMP
ARA
T
OR
MA
TCH
CONTROL
TRIGGER
AND
EVENT CONTROL
REQUESTS
REGISTERS
TRIG
PROFILE
OUTPUT
EXTERNAL EVENT
