Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
418
Freescale Semiconductor
Please see also the detailed conversion flow control bit mandatory requirements and execution information
for bit RSTA and SEQA described in
Section 10.5.3.2.5, “The four ADC conversion flow control bits
.
10.8.8
Continuous Conversion
Applications that only need to continuously convert a list of channels, without the need for timing control
or the ability to perform different sequences of conversions (grouped number of different channels to
convert) can make use of the following simple setup:
•
“Trigger Mode” configuration
•
Single buffer CSL
•
Depending on data transfer rate either use single or double buffer RVL configuration
•
Define a list of conversion commands which only contains the “End Of List” command with
automatic wrap to top of CSL
After finishing the configuration and enabling the ADC an initial Restart Event is sufficient to launch the
continuous conversion until next device reset or low power mode.
In case a Low Power Mode is used:
If bit AUT_RSTA is set before Low Power Mode is entered the conversion continues automatically as
soon as a low power mode (Stop Mode or Wait Mode with bit SWAI set) is exited.
Figure 10-41. Conversion Flow Control Diagram — Continuous Conversion (with Stop Mode)
CSL_0
Active
AN3 AN1 AN4 IN5
Initial
Restart
Event
EOL
AN3 AN1 AN4 IN5
EOL
AN3 AN1
Stop Mode request,
Automatic Sequence Abort
Event
Idle
Stop Mode
entry
Wake-up
Event with
Idle
AUT_RSTA
Active
AN3 AN1 AN4
Abort
t
