Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
404
Freescale Semiconductor
10.5.3.2.4
The two conversion flow control Mode Configurations
The ADC provides two modes (“Trigger Mode” and “Restart Mode”) which are different in the conversion
control flow. The “Restart Mode” provides precise timing control about the sample start point but is more
complex from the flow control perspective, while the “Trigger Mode” is more simple from flow control
point of view but is less controllable regarding conversion sample start.
Following are the key differences:
In “Trigger Mode” configuration, when conversion flow control bit RSTA gets set the bit TRIG gets set
automatically. Hence in “Trigger Mode” the applications should not set the bit TRIG and bit RSTA
simultaneously (via data bus or internal interface), because it is a flow control failure and the ADC will
cease operation.
In “Trigger Mode” configuration, after the execution of the initial Restart Event the current CSL can be
executed and controlled via Trigger Events only. Hence, if the “End Of List” command is reached a restart
of conversion flow from top of current CSL does not require to set bit RSTA because returning to the top
of current CSL is done automatically. Therefore the current CSL can be executed again after the “End Of
List” command type is executed by a Trigger Event only.
In “Restart Mode” configuration, the execution of a CSL is controlled via Trigger Events and Restart
Events. After execution of the “End Of List” command the conversion flow must be continued by a Restart
Event followed by a Trigger Event and the Trigger Event must not occur before the Restart Event has
finished.
For more details and examples regarding flow control and application use cases please see following
section and
Section 10.8.7, “Conversion flow control application information
.
10.5.3.2.5
The four ADC conversion flow control bits
There are four bits to control conversion flow (execution of a CSL and CSL exchange in double buffer
mode). Each bit is controllable via the data bus and internal interface depending on the setting of
ACC_CFG[1:0] bits (see also
). In the following the conversion control event to control the
conversion flow is given with the related internal interface signal and corresponding register bit name
together with information regarding:
— Function of the conversion control event
— How to request the event
— When is the event finished
— Mandatory requirements to executed the event
A summary of all event combinations is provided by
.
•
Trigger Event
Internal Interface Signal: Trigger
Corresponding Bit Name: TRIG
