Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
Freescale Semiconductor
261
7.3.2.15
Low Voltage Control Register (CPMULVCTL)
The CPMULVCTL register allows the configuration of the low-voltage detect features.
Read: Anytime
Write: LVIE and LVIF are write anytime, LVDS is read only
Module Base + 0x0011
7
6
5
4
3
2
1
0
R
0
0
0
0
0
LVDS
LVIE
LVIF
W
Reset
0
0
0
0
0
U
0
U
The Reset state of LVDS and LVIF depends on the external supplied VDDA level
= Unimplemented or Reserved
Figure 7-19. Low Voltage Control Register (CPMULVCTL)
Table 7-18. CPMULVCTL Field Descriptions
Field
Description
2
LVDS
Low-Voltage Detect Status Bit
— This read-only status bit reflects the voltage level on VDDA.
Writes have no
effect.
0 Input voltage VDDA is above level V
LVID
or RPM.
1 Input voltage VDDA is below level V
LVIA
and FPM.
1
LVIE
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
0
LVIF
Low-Voltage Interrupt Flag
— LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1.
Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
