Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 17 Stepper Stall Detector (SSDV2) Block Description
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 625
17.3.2.1 Return-to-Zero Control Register (RTZCTL)
Read: anytime
Write: anytime
Module Base + 0x0000
7 6 5 4 3 2 1 0
R
ITG DCOIL RCIR POL
0 0
STEP
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 17-2. Return-to-Zero Control Register (RTZCTL)
Table 17-4. RTZCTL Field Descriptions
Field Description
7
ITG
Integration — During return to zero (RTZE = 1), one of the coils must be recirculated or non-driven determined
by the STEP field. If the ITG bit is set, the coil is non-driven, and if the ITG bit is clear, the coil is being recirculated.
Table 17-5 shows the condition state of each transistor from Figure 17-1 based on the STEP, ITG, DCOIL and
RCIR bits.
Regardless of the RTZE bit value, if the ITG bit is set, one end of the non-driven coil connects to the (non-zero)
reference input and the other end connects to the integrator input of the sigma-delta converter. Regardless of the
RTZE bit value, if the ITG bit is clear, the non-driven coil is in a blanking state, the converter is in a reset state,
and the accumulator is initialized to zero.
Table 17-6 shows the condition state of each switch from Figure 17-1
based on the ITG, STEP and POL bits.
0 Blanking
1 Integration
6
DCOIL
Drive Coil — During return to zero (RTZE=1), one of the coils must be driven determined by the STEP field. If
the DCOIL bit is set, this coil is driven. If the DCOIL bit is clear, this coil is disconnected or drivers turned off.
Table 17-5 shows the condition state of each transistor from Figure 17-1 based on the STEP, ITG, DCOIL and
RCIR bits.
0 Disconnect Coil
1 Drive Coil
5
RCIR
Recirculation in Blanking Mode — During return to zero (RTZE = 1), one of the coils is recirculated prior to
integration during the blanking period. This bit determines if the coil is recirculated via VDDM or via VSSM.
Table 17-5 shows the condition state of each transistor from Figure 17-1 based on the STEP, ITG, DCOIL and
RCIR bits.
0 Recirculation on the high side transistors
1 Recirculation on the low side transistors
4
POL
Polarity — This bit determines which end of the non-driven coil is routed to the sigma-delta converter during
conversion or integration mode. Table 17-6 shows the condition state of each switch from Figure 17-1 based on
the ITG, STEP and POL bits.
1:0
STEP
Full Step State — This field indicates one of the four possible full step states. Step 0 is considered the east pole
or 0

angle, step 1 is the north Pole or 90

angle, step 2 is the west pole or 180

angle, and step 3 is the south
pole or 270

angle. For each full step state, Table 17-7 shows the current through each of the two coils, and the
coil nodes that are multiplexed to the sigma-delta converter during conversion or integration mode.