Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
367
10.4.2.3
ADC Status Register (ADCSTS)
It is important to note that if flag DBECC_ERR is set the ADC ceases operation. In order to make the ADC
operational again an ADC Soft-Reset must be issued. An ADC Soft-Reset clears bits CSL_SEL and
RVL_SEL.
Read: Anytime
Write:
•
Bits CSL_SEL and RVL_SEL anytime if bit ADC_EN is clear or bit SMOD_ACC is set
•
Bits DBECC_ERR and READY not writable
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
CSL_SEL
RVL_SEL
DBECC_ERR
Reserved
READY
0
0
0
W
Reset
0
0
0
0
1
0
0
0
= Unimplemented or Reserved
Figure 10-6. ADC Status Register (ADCSTS)
Table 10-5. ADCSTS Field Descriptions
Field
Description
7
CSL_SEL
Command Sequence List Select bit
— This bit controls and indicates which ADC Command List is active. This
bit can only be written if ADC_EN bit is clear. This bit toggles in CSL double buffer mode when no conversion or
conversion sequence is ongoing and bit LDOK is set and bit RSTA is set. In CSL single buffer mode this bit is
forced to 1’b0 by bit CSL_BMOD.
0 ADC Command List 0 is active.
1 ADC Command List 1 is active.
6
RVL_SEL
Result Value List Select Bit
— This bit controls and indicates which ADC Result List is active. This bit can only
be written if bit ADC_EN is clear. After storage of the initial Result Value List this bit toggles in RVL double buffer
mode whenever the conversion result of the first conversion of the current CSL is stored or a CSL got aborted.
In RVL single buffer mode this bit is forced to 1’b0 by bit RVL_BMOD.
Please see also
Section 10.2.1.2, “MCU Operating Modes
for information regarding Result List usage in case of
Stop or Wait Mode.
0 ADC Result List 0 is active.
1 ADC Result List 1 is active.
5
DBECC_ERR
Double Bit ECC Error Flag
— This flag indicates that a double bit ECC error occurred during conversion
command load or result storage and ADC ceases operation.
In order to make the ADC operational again an ADC Soft-Reset must be issued.
This bit is cleared if bit ADC_EN is clear.
0 No double bit ECC error occurred.
1 A double bit ECC error occurred.
3
READY
Ready For Restart Event Flag
— This flag indicates that ADC is in its idle state and ready for a Restart Event.
It can be used to verify after exit from Wait Mode if a Restart Event can be issued and processed immediately
without any latency time due to an ongoing Sequence Abort Event after exit from MCU Wait Mode (see also the
Note in
Section 10.2.1.2, “MCU Operating Modes
0 ADC not in idle state.
1 ADC is in idle state.
